Impedance.ppt

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1、阻抗控制設計與運用TAPOWER/GROUNDSIGNALWSIGNALWTAADPOWER/GROUNDPOWER/GROUND在磁場區裡之條線(STRIPLINE)磁場靜電場*注意:當電流流動時其磁場就產生.當有電壓時其靜電場就產生.*注意:當電流流動時其磁場就產生.當有電壓時其靜電場就產生.NoiseSourceinanEcl.BasedSystem(34%)(5%)(16%)(5%)(16%)(7%)(8%)(9%)TotalofAllNoiseSources=224mVAvailableNoiseBudget=125mVE

2、xcessNoise=99mVImpedanceMismatchSourcesChangesintracewidthStubsLoadsConnectortransitionsPoorlymatchedterminationsorlackofterminationsLargepowerplanediscontinuitiesInotherwords,anythingthatcanchangetheLoorCoofatransmissionlinewillchangeitsimpedance.NOTE:Inspiteof

3、popularheldbeliefs,viasandrightanglebendsarenotmeasuresourcesofimpedancemismatch.阻抗控制需求決定條件工作頻率(影響risetime)傳輸線之長度(造成propagationdelay)所以工作頻率越高,傳輸線過長需考慮作阻抗控制.所以工作頻率越高,傳輸線過長需考慮作阻抗控制.WhenisReflectionImportant?Reflectionscanusuallybeignoredwhentherisetimeofasignalis

4、slowrelativetopropagationdelayRuleofthumb-Whentherisetimeisshorterthanabout8timesthepropagationdelay,transmissionlineeffectsbecomesignificant.Thatis,ifRiseTimePropagationDelay≦8RiseTimeandPropagationDelayExamples#1-10Nsrisetime(typicalTTL)-1Nsinterconnectdelay(~6inche

5、s)10ns1nsNoProblemRiseTimeandPropagationDelayExamples#2-0.5Nsrisetime(ECLoradvancedCMOSLogic)-1Nsinterconnectdelay(~6inches)Reflectionoccuratanyrisetime,however,atslowerrisetimestheynotbesignificantinthecircuit0.5ns1nsReflection傳輸線構成之三要素訊號線介質層接地層++傳輸線傳輸線構成之三要素傳輸線構成之三要素

6、阻抗匹配之三個要素輸出阻抗(原始主動零件)特性阻抗(訊號線)輸入阻抗(被動零件)阻抗匹配(ImpedanceMatch)sourceP.C.B.LOAD阻抗匹配之三個要素阻抗匹配之三個要素阻抗控制設計流程圖(ImpedanceControlDesignFlowChart)資料接收(Datacome-in)阻抗控制設計(ImpedanceControl)製作規範填寫(Run-CardIssue)底片設計(A/WDesign)基板,膠片管制(Material,PrepergControl)壓合厚度管制(LaminateThickness

7、Control)電鍍厚鍍管制(PlatingThicknessControl)阻抗量測(ImpedanceMeasurement)線寬蝕刻管制(LineWidthEtchingControl)Micro-strip-lineStrip-lineDual-strip-lineEmbededmicro-strip-lineMicrosectionInspectionMicrosectionInspectionMicrosectionInspectionT.D.R.Measurement名詞定義:何謂“特性阻抗值”(Characteri

8、sticImpedance,ZO)所用單位為歐姆(ohm;Ω).電子機器傳輸訊號線中,其高頻訊號或電磁波傳播時所遭遇的阻力稱之為特性阻抗.與其電感及電容都有關係,即Zo=√L/CL:電感C:電容名詞定義:意指PCB之外層Tra