PLD与数字系统设计2.ppt

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1、PLD与数字系统设计(2)中国科学技术大学电子科学与技术系主讲教师：李辉1WhatisFPGA?FPGAsareprogrammabledevicesthatcanbedirectlyconfiguredbytheenduserwithouttheuseofanintegratedcircuitfabricationfacility.Theyofferthedesignerthebenefitsofcustomhardware,eliminatinghighdevelopmentcostsandmanuf

2、acturingtime.2WhatisFPGA?Theywerefirstintroducedin1985byXilinx.Sincethen,manydifferentFPGAshavebeendevelopedbynumberofcompaniessuchasAT&T,Actel,Altera,Motorola,QuickLogic,andCrosspointSolutions.3WhatisFPGA?FigureshowsaconceptualdiagramofatypicalFPGA.4What

3、isFPGA?AllXilinxFPGAscontainthesamebasicresourcesSlices(groupedintoCLBs)ContaincombinatoriallogicandregisterresourcesIOBsInterfacebetweentheFPGAandtheoutsideworldProgrammableinterconnectOtherresourcesMemoryMultipliersGlobalclockbuffersBoundaryscanlogic51.

4、3.2SpartanFPGACMOS+SRAMTechnology6SRAM78Structure9LUT10CLB11I/OB1213141.3.3Spartan-II15Spartan-IIStructure16CLBResources17CLBResources18CLBResources19CLBResources20CLBResources21CLBResources(1)22CLBResourcesxc2s15-6-vq100CellUsage:#BELS(ABasicElement):3#L

5、UT4:1#MUXF5:1#VCC:1#FlipFlops/Latches:1#FDCE:123CLBResourcesTheFDCEisanasynchronouslycleared,enabledD-typeflip-flop.24CLBResources(2)25CLBResourcesxc2s15-6-vq100CellUsage:#BELS:3#LUT4:1#MUXF5:1#VCC:1#FlipFlops/Latches:1#FDRE:126CLBResourcesFDREisaD-typefl

6、ip-flopwithdata(D),clockenable(CE),andsynchronousreset(R)inputsanddataoutput(Q).27CLBResources(3)28CLBResourcesxc2s15-6-vq100CellUsage:#BELS:1#LUT4:1#FlipFlops/Latches:1#FDSE:129CLBResourcesFDRSEisasingleD-typeflip-flopwithsynchronousreset(CLR),synchronou

7、sset(PRE),andclockenable(CE)inputsanddataoutput(Q).30ProgrammableI/OStandards31ProgrammableI/OStandards32ProgrammableI/OStandards33ProgrammableI/OStandards34ProgrammableI/OStandards寄存器驻留在I/O单元35ProgrammableI/OStandards36ProgrammableI/OStandards37Programma

8、bleI/OStandards•Eachbankhasainputreferencevoltage(VREF).–SharedamongallI/Osinthebank.–AllI/OtypesinabankmustusethesameVREF.–AllVREFpinsinabankmustbetiedtogether.•InputsnotrequiringaVREFfitinthebank.–LVTTL,LVCMOS,LVP