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《基于fpga的数字密码锁(使用矩阵键盘)》由会员上传分享，免费在线阅读，更多相关内容在行业资料-天天文库。
1、..基于FPGA数字密码锁板子使用的是DE2顶层topmodulelock(reset,clk,row,col,mm0,mm1,mm2,mm3,led1,led2,led3,set_flog);inputclk,reset;input[3:0]row;outputwire[3:0]col;outputwire[6:0]mm0,mm1,mm2,mm3;outputregled1,led2,led3;wire[3:0]key_value;reg[3:0]temp_key;reg[3:0]m0,m1,m2,m3;reg[3:0]m_
2、0,m_1,m_2,m_3;reg[5:0]state;reg[2:0]wei;wirekey_valid;reg[1:0]count_wrong;outputregset_flog;parametervalid=6'b000000,set=6'b000001,collection_mm=6'b000010,cmd=6'b000100,collection=6'b001000,wrong=6'b010000,correct=6'b100000,die_lock=6'b000011,lock=6'b000111;always@(
3、posedgeclkornegedgereset)beginif(!reset)beginstate<=6'b000000;wei<=0;led3<=0;set_flog<=0;led1<=0;led2<=0;m0<=15;m1<=15;m2<=15;m3<=15;endelsebegincase(state)valid:if(key_valid)word教育资料..begintemp_key<=key_value;state<=collection;endelsestate<=valid;collection:beginif
4、(key_value>=0&&key_value<=9)beginif(led1&&(!set_flog))//开启状态不能按数字键state<=valid;elseif((!key_valid)&&(wei<5))beginled2<=0;state<=collection_mm;wei<=wei+1'b1;endelsestate<=collection;endelseif(!key_valid)state<=cmd;endcollection_mm:begincase(wei)1:m0<=temp_key;2:m1<=t
5、emp_key;3:m2<=temp_key;4:m3<=temp_key;endcasestate<=valid;endcmd:begincase(temp_key)15:if(!led1)beginm0<=15;m1<=15;m2<=15;m3<=15;//*clearword教育资料..state<=valid;wei<=0;led2<=0;led1<=0;endelsestate<=valid;14:if(led1)state<=valid;elseif(wei)//backdeletebegincase(wei)1:
6、m0<=15;2:m1<=15;3:m2<=15;4:m3<=15;endcasewei<=wei-1'b1;state<=valid;led2<=0;endelsestate<=valid;13:if(set_flog)//保存密码beginset_flog<=0;led1<=0;m_0<=m0;m_1<=m1;m_2<=m2;m_3<=m3;state<=lock;endelseif((m0==m_0)&&(m1==m_1)&&(m2==m_2)&&(m3==m_3))//comparebeginstate<=correc
7、t;m0<=15;m1<=15;m2<=15;m3<=15;endelsebeginstate<=wrong;count_wrong<=count_wrong+1;endword教育资料..12:state<=lock;10:if(led1)//setbeginset_flog<=1;wei<=0;m0<=15;m1<=15;m2<=15;m3<=15;state<=valid;enddefault:state<=valid;endcaseendcorrect:begin//openled1<=1;state<=valid;c
8、ount_wrong<=0;endwrong:beginled2<=1;state<=valid;led1<=0;if(count_wrong==3)//lockdiebegincount_wrong<=0;state<=die_lock;endendlock:beginle
