附录-数电常用管脚内部逻辑图

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1、附录部份集成电路引脚排列一．74系列部份集成电路引脚图74ls002输入四与非门74ls012输入四与非门(oc)74ls04六倒相器74ls022输入四或非门74ls082输入四与门74ls103输入三与非门1074ls113输入三与门74ls204输入双与非门74ls214输入双与门74ls273输入三或非门74ls308输入与非门74ls322输入四或门1074ls48bcd-七段译码器/驱动器74ls854位数字比较器74ls862输入四异或门74ls90十进制计数器74ls112负沿触发双j-k触发器(带预置端和清除端)7

2、4ls1383-8线译码器/多路转换器1074ls1488线-3线八进制优先编码器74ls160可预置十进制计数器(异步清除)74ls161可预置四位二进制计数器(并清除异步)74ls163可预置四位二进制计数器(并清除异步)74ls1648位并行输出串行移位寄存器74ls175四d触发器74ls175功能表1074ls190同步可逆计数器(bcd,二进制)74ls192同步可逆计数器74ls194四位双向通用移位寄存器74ls373八d锁存器74ls373功能表10二．CMOS集成电路引脚图4001　四2输入或非门4002　双4输

3、入或非门4011　四2输入与非门4012双4输入与非门Y=/ABCD4013双D型触发器（带预置和清除端）40148位串入/并入—串出移位寄存器104025三3输入或非门4027双J-K主从触发器（带置位和复位端）4028BCD—十进制译码器4030四异或门输入输出SRENQ××L高阻LLH不变HLHHLHHLHHH不定4043　四或非R─S（三态）4043功能表104068　8输入与非/与门4069六反相器4070　四异或门4071　四2输入或门4072　双4输入或门4073　三3输入与门4081　四2输入与门104082　双4输

4、入与门40106　六施密特触发器（反相）40192、40193　可预置可逆计数器（双时钟）4514、4515　4位锁存/4－16线译码器4515输出H电平有效，4515输出L电平有效。4518　双BCD同步加计数器4553三数字BCD计数器10目录实验箱简介························································1第一部分基本单元实验实验一　TTL集成逻辑门的逻辑功能与参数测试·································4实验二　CMOS集成逻辑门的逻辑功

5、能与参数测试····················11实验三组合逻辑电路的设计与测试······························14实验四译码器及其应用········································17实验五数据选择器及其应用····································24实验六触发器及其应用········································30实验七　计数器及其应用·····························

6、···········37实验八　移位寄存器及其应用····································43实验九自激多谐振荡器·········································50实验十　单稳态触发器与施密特触发器·····························53实验十一555时基电路及其应用································58第二部分综合性实验实验十二智力竞赛抢答器···································

7、·····63实验十三电子秒表···············································65实验十四电子密码锁···············································70实验十五数字钟················································72第三部分课程设计实验十六简易脉宽设计电路·····································74实验十七　数字频率计·····················

8、························77实验十八拔河游戏机··········································82附录部份集成电路引脚排列··························