显示模块设计

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1、5.译码模块设计与仿真译码程序将输入的用来显示的两位倒计时数值，分解成四个整形的数值，以供后面的译码显示模块继续译码显示。译码程序清单如下：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityto8421bcdisport(at,bt:inintegerrange0to80;aout1,aout2,bout1,bout2:outintegerrange0to9);endto8421bcd;archi

2、tectureaofto8421bcdisbeginprocess(at,bt)beginifat>=70thenaout1<=7;aout2<=at-70;elsifat>=60thenaout1<=6;aout2<=at-60;elsifat>=50thenaout1<=5;aout2<=at-50;elsifat>=40thenaout1<=4;aout2<=at-40;elsifat>=30thenaout1<=3;aout2<=at-30;elsifat>=20thenaout1<=2;

3、aout2<=at-20;elsifat>=10thenaout1<=1;aout2<=at-10;elsifat>=0thenaout1<=0;aout2<=at;endif;ifbt>=70thenbout1<=7;bout2<=bt-70;elsifbt>=60thenbout1<=6;bout2<=bt-60;elsifbt>=50thenbout1<=5;bout2<=bt-50;elsifbt>=40thenbout1<=4;bout2<=bt-40;elsifbt>=30thenbo

4、ut1<=3;bout2<=bt-30;elsifbt>=20thenbout1<=2;bout2<=bt-20;elsifbt>=10thenbout1<=1;bout2<=bt-10;elsifbt>=0thenbout1<=0;bout2<=bt;endif;endprocess;enda;译码程序仿真结果如图1-5所示：图1-5译码程序仿真结果图在译码程序仿真结果图中，at,bt为输入信号，at，bt的范围为0~80。这包含了所有倒计时的范围；aout1，aout2，bout1，bout2

5、为输出信号，值的范围为0~9，涵盖了数码管显示数字的范围。图中at，bt的值不断变化，而aout1，aout2都能将at的值分解成个位和十位，其中aout1代表十位，aout2代表个位；bout1，bout2都能将bt的值分解成个位和十位，其中bout1代表十位，bout2代表个位。仿真结果完全正确，符合预期。6.译码显示模块设计与仿真译码显示模块将上一个模块输出四个一位数译码成相对应的七位数码管段码，完成倒计时的译码和显示。译码显示程序清单如下：libraryieee;useieee.std_l

6、ogic_1164.all;useieee.std_logic_unsigned.all;entityyimaxianshiisport(at1,at2,bt1,bt2:inintegerrange0to9;aout1,aout2,bout1,bout2:outstd_logic_vector(7downto0));endyimaxianshi;architectureaofyimaxianshiisbeginprocess(at1,at2,bt1,bt2)begincaseat1iswhen0=

7、>aout1<="00111111";when1=>aout1<="00000110";when2=>aout1<="01011011";when3=>aout1<="01001111";when4=>aout1<="01100110";when5=>aout1<="01101101";when6=>aout1<="01111101";when7=>aout1<="00000111";when8=>aout1<="01111111";when9=>aout1<="01101111";whenoth

8、ers=>aout1<="00000000";endcase;caseat2iswhen0=>aout2<="00111111";when1=>aout2<="00000110";when2=>aout2<="01011011";when3=>aout2<="01001111";when4=>aout2<="01100110";when5=>aout2<="01101101";when6=>aout2<="01111101";when7=>aout2<="00000111";whe