testbanch+Verilog在Modelsim实现3分频及5分频

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1、用Verilog语言写的三分频电路//上升沿触发的分频设计modulethree(clkin,clkout);inputclkin;//定义输入端口outputclkout;//定义输出端?reg[1:0]step1,step;always@(posedgeclkin)begincase(step)2'b00:step<=2'b01;2'b01:step<=2'b10;2'b10:step<=2'b00;default:step<=2'b00;endcaseendalways@(negedgeclkin)begincase(step1)2'b00:step1<=2'b01;2'b01:st

2、ep1<=2'b10;2'b10:step1<=2'b00;default:step1<=2'b00;endcaseendassignclkout=~(step[1]

3、step1[1]);endmoduleTestbanch：`timescale1ns/100psmodulediv3_tb;wireclkout;regclkin;wire[1:0]step1,step;initialbeginclkin=0;endalways#2clkin=~clkin;div3DUT(.clkin(clkin),.clkout(clkout),.step1(step1),.step(step));end

4、module用Verilog语言写五分频电路，占空比为50％：modulediv_5(clkin,rst,clkout);inputclkin,rst;outputclkout;reg[2:0]step1,step2;always@(posedgeclkin)if(!rst)step1<=3'b000;elsebegincase(step1)3'b000:step1<=3'b001;3'b001:step1<=3'b011;3'b011:step1<=3'b100;3'b100:step1<=3'b010;3'b010:step1<=3'b000;default:step1<=3'b000

5、;endcaseendalways@(negedgeclkin)if(!rst)step2<=3'b000;elsebegincase(step2)3'b000:step2<=3'b001;3'b001:step2<=3'b011;3'b011:step2<=3'b100;3'b100:step2<=3'b010;3'b010:step2<=3'b000;default:step2<=3'b000;endcaseendassignclkout=step1[0]

6、step2[0];endmoduleTestbanch：modulediv5_tb;regrst;regclkin;wireclk

7、out;wire[2:0]step1,step2;initialbeginclkin=0;endalways#10clkin=~clkin;initialbeginrst=0;#20rst=1;#2000$finish;enddiv5DUT(.rst(rst),.clkin(clkin),.clkout(clkout),.step1(step1),.step2(step2));Endmodule