Notebook_硬件架构

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1、HWQA培訓教材之硬體架构篇1InventecConfidential2021/7/15M/BHARDWAREDESCRIPTIONPChardwarearchitectureSignalintegritydescriptionCircuitdesignconceptPCIbusCacheICpackmodeHWQA培訓教材PChardwarearchitecturePC硬體架构HWQA培訓教材PChardwarearchitectureI.M/BblockdiagramBIOS/FLASHROMSUPERI/OCTRLISABUSSouthBrid

2、geCDROMPCIBUSISASLOT1VGACTRL66/100MHZNorthBridge66/100MHZ33MHZSLOT1DIMMVIDEOSGRAMMTRISADRIVEISASLOT2PCIDEVICECPU33MHZPCISLOTSHDDUSBAGPBUS(Example1)1HWQA培訓教材PChardwarearchitecturePChardwarearchitecturePChardwarearchitecturePChardwarearchitecturePChardwarearchitecture.CPU:Central

3、processorunit.L1cacheinside..Hostbus:BusconnectedtoCPU..Northbridge:HosttoPCIbridge.Memorycontrollerinside..DIMM:Dual-in-linememorymodule..VGAcontroller:ShowscontentsofvideoRAMondisplay..Southbridge:PCItoISAbridge.Interrupt,DMA,Timer.PCIbus:33MHz,32-bitmultiplexedaddress/databu

4、s..ISAbus:24-bitaddressbus,16-bitdatabus..SuperI/O:FDC,SIO,PIO,KBC,RTC/CMOSinside..ROMBIOS:System&videoBIOSfirmwarecodesinside.2PChardwarearchitecturePPGA370CPUGMCHGraphicMemoryControlHubICHI/OControlHubSuperI/OController.FirmwareHubSDRAMModules.PCIBUSHDDCD-ROMUSBPCISlotsVIDEOC

5、ACHEPCIDEVICECRT(Example2)LPCI/F3PChardwarearchitecture.GMCH:Graphics&memorycontrollerhub.ICH:I/Ocontrollerhub.WithPCI&LPCinterface..FWH:Firmwarehub..LPCI/F:Lowpincountinterface.4PChardwarearchitectureII.Busconcept1.Busmaster:Devicewhichownscontrolofabusandiscapableofissuingcom

6、mands&targetaddressduringamastercycle.2.Target(slave)device:Devicewhichcorrespondstothetargetaddressofabuscycleandoperatesbasedonthecommandsfrombusmaster.5PChardwarearchitecture3.Buscyclea.Memoryreadcycle:CPU(orbusmaster)readsdatafrommemoryb.Memorywritecycle:CPU(orbusmaster)wri

7、tesdatatomemoryc.I/Oreadcycle:CPU(orbusmaster)readsdatafromI/Odeviced.I/Owritecycle:CPU(orbusmaster)writesdatatoI/Odevicee.DMAcycle:DataistransferredbetweenI/Odevice&memorydirectlyundercontrolofDMAcontrollerwithoutCPUintervention.6PChardwarearchitectureIII.DMAchannelsDMAchannel

8、0:8-bitDMAchannel1:8-bitDMAchannel2:8-bit,FDCDMAchanne