数字电压表VHDL程序

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1、数字电压表数字电压表设计简易数字电压表数字电压表的设计单片机数字电压表数字电压表的发展数字电压表发展数字电压表原理数字电压表论文程序如下：LIBRARYieee;--A/D0809useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityadisport(ST,eoc:instd_logic;--控制端口d:instd_logic_vector(7downto0);oe,st

2、a,ale,adda:outstd_logic;q:outstd_logic_vector(7downto0));endad;architectureaofadistypestatesis(st0,st1,st2,st3,st4,st5,st6);--7个状态signalc_state,n_state:states:=st0;signalregl:std_logic_vector(7downto0);signallock:std_logic;beginadda<='1';com:process(c_

3、state,eoc)begincasec_stateiswhenst0=>ale<='0';sta<='0';oe<='0';lock<='0';n_state<=st1;whenst1=>ale<='1';sta<='0';oe<='0';lock<='0';n_state<=st2;whenst2=>ale<='0';sta<='1';oe<='0';lock<='0';n_state<=st3;whenst3=>ale<='0';sta<='0';oe<='0';lock<='0';if(eo

4、c='1')thenn_state<=st4;elsen_state<=st3;――eoc为‘1’转换结束进入下一状态endif;――否则继续转换whenst4=>ale<='0';sta<='0';oe<='1';lock<='0';n_state<=st5;whenst5=>ale<='0';sta<='0';oe<='0';lock<='1';n_state<=st6;whenst6=>ale<='0';sta<='0';oe<='0';lock<='1';n_state<=st0;wheno

5、thers=>n_state<=st0;endcase;endprocesscom;reg:process(st)beginif(st'eventandst='1')thenc_state<=n_state;endif;endprocessreg;lo:process(lock)--锁存beginif(lock'eventandlock='1')thenregl<=d;endif;endprocesslo;q<=regl;enda;――BCD8位转12LIBRARYIEEE;USEIEEE.STD_

6、LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYBCDISPORT(V:INSTD_LOGIC_VECTOR(7DOWNTO0);HB,LB:BUFFERSTD_LOGIC_VECTOR(11DOWNTO0);BVALUE:BUFFERSTD_LOGIC_VECTOR(11DOWNTO0);BCD_L,BCD_M,BCD_H:OUTSTD_LOGIC_VECTOR(3DOWNTO0));E

7、NDBCD;ARCHITECTUREAOFBCDISBEGINP1:PROCESS(V(7DOWNTO4))BEGIN--A/D输出高4位转换分辨率0.32VIFV(7DOWNTO4)="1111"THENHB<="010010000000";--4.80VELSIFV(7DOWNTO4)="1110"THENHB<="010001001000";--4.48VELSIFV(7DOWNTO4)="1101"THENHB<="010000010110";--4.16VELSIFV(7DOWNTO4)=

8、"1100"THENHB<="001110000100";--3.84VELSIFV(7DOWNTO4)="1011"THENHB<="001101010010";--3.52VELSIFV(7DOWNTO4)="1010"THENHB<="001100100000";--3.20VELSIFV(7DOWNTO4)="1001"THENHB<="001010001000";--2.88VELSIFV(7DOWNTO4)="1000"THENHB<="001001010