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1、CD4051B,CD4052B,CD4053BDatasheetacquiredfromHarrisSemiconductorAugust1998-RevisedMarch2000SCHS047DCMOSAnalogMultiplexers/DemultiplexersFeatureswithLogicLevelConversion•WideRangeofDigitalandAnalogSignalLevelsTheCD4051B,CD4052B,andCD4053Banalogmultiplexers-Digital........
2、......................3Vto20Varedigitally-controlledanalogswitcheshavinglowON-Analog...............................£20VP-P[/TitleimpedanceandverylowOFFleakagecurrent.Controlof•LowONResistance,125W(Typ)Over15VP-PSignalInputanalogsignalsupto20VP-PcanbeachievedbydigitalRan
3、geforVDD-VEE=18V(CD405signalamplitudesof4.5Vto20V(ifVDD-VSS=3V,a1B,•HighOFFResistance,ChannelLeakageof±100pA(Typ)VDD-VEEofupto13Vcanbecontrolled;forVDD-VEElevelatVDD-VEE=18VCD4052differencesabove13V,aVDD-VSSofatleast4.5VisB,required).Forexample,ifVDD=+4.5V,VSS=0V,and•Lo
4、gic-LevelConversionforDigitalAddressingSignalsofCD4053VEE=-13.5V,analogsignalsfrom-13.5Vto+4.5Vcanbe3Vto20V(VDD-VSS=3Vto20V)toSwitchAnalogcontrolledbydigitalinputsof0Vto5V.ThesemultiplexerSignalsto20VP-P(VDD-VEE=20V)B)circuitsdissipateextremelylowquiescentpoweroverthe•M
5、atchedSwitchCharacteristics,rON=5W(Typ)for/Sub-fullVDD-VSSandVDD-VEEsupply-voltageranges,VDD-VEE=15Vjectindependentofthelogicstateofthecontrolsignals.When•VeryLowQuiescentPowerDissipationUnderAllDigital-(CMOSalogic“1”ispresentattheinhibitinputterminal,allControlInputand
6、SupplyConditions,0.2mW(Typ)atAnalogchannelsareoff.VDD-VSS=VDD-VEE=10VMulti-TheCD4051Bisasingle8-Channelmultiplexerhavingthree•BinaryAddressDecodingonChipplex-binarycontrolinputs,A,B,andC,andaninhibitinput.The•5V,10Vand15VParametricRatingsers/Demthreebinarysignalsselect1
7、of8channelstobeturnedon,ultiplex-andconnectoneofthe8inputstotheoutput.•10%TestedforQuiescentCurrentat20VerswithTheCD4052Bisadifferential4-Channelmultiplexerhaving•MaximumInputCurrentof1mAat18VOverFullPackageoLogictwobinarycontrolinputs,AandB,andaninhibitinput.TheTempera
8、tureRange,100nAat18Vand25CLeveltwobinaryinputsignalsselect1of4pairsofchannelstobe•Break-Before-MakeSwitchingEl
