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1、【例1】调用门元件实现的1位半加器moduleha丄f_addl(a,bzsum,cout);inputa,b;outputsum,cout;and(cout,a,b);xor(sum,azb);endmodule【例2】数据流方式描述的1位半加器modulehalf_add2(a,bzsum,cout);inputoutputsum,cout;assignsum=aAb;assigncout=a&b;endmodule【例3】采用行为描述的1位半加器modulehalf_add3(a,bzsum
2、,cout);inputa,b;outputsum,cout;regsum,cout;always@(aorb)begincase(-2,b})//真值表描述2fb00:beginsum=0;cout=0;end2-b01:beginsum=l;cout=0;end2-blO:beginsum=l;cout=0;end2fbll:beginsum=0;cout=l;endendcaseendendmodule【例4】采用行为描述的1位半加器moduleha丄f_add4(a,bzsum,cout)
3、;inputa,b;outputsum,cout;regsum,cout;always@(aorb)beginsum=aAb;cout=u&b;endendmodule【例5】调用门元件实现的1位全加器modulefull_addl(a,bzcin,sum,cout);input,cin;outputsum,cout;wiresl,mlzm2,m3;and(ml,a,b),(m2,b,cin),(m3,a,cin);xor(si,a,b),(sum,slzcin);or(cout,ml,m2,m3
4、);endmodule【例6】数据流描述的1位全加器modulefull_add2(afb,cinzsum,cout);inputa,bzcin;outputsum,cout;assignsum=aAbAcin;assigncout=(3&b)I(b&cin)
5、(cin&a);endmodule【例7】1位全加器modulefull_add3(a,bzcin,sum,cout);inputa,bzcin;outputsum,cout;assign{cout,sum}=a+b+cin;endmodu
6、le【例8】行为描述的1位全加器modulefull_add4(a,b,cin,sum,cout);inputa,bzcin;outputsum,cout;regsum,cout;//在always块中被賦值的变量应定狡为reg型regml,m2,m3;always@(aorborcin)beginsum=(aAb)Acin;ml=a&b;m2=b&cin;m3=a&cin;cout=end(ml
7、m2)
8、m3;endmodule40]b(o]5um[0]sum[IJsum[3]sum[2]【例9
9、】结构描述的4位级连全加器includenfull_addl.vnmoduleadd4_l(sum,cout,a,b,cin);output[3:0]sum;outputcout;input[3:0Ja,b;inputcin;full_addlf0(a[0],b[0],oinzsum[0],cinl);//级连描述full._addlfl(a[l],b[l],oinl,sum[l],cin2);full._addlf2(a[2]zb[2]zcin2zsum[2],cin3);full._addlf
10、3(a[3],b[3],cin3,sum[3],cout);endmodule【例10】数据流描述的4位全加器moduleadd4_2(cout,sum,a,output[3:0]sum;outputcout;input[3:0]a,b;inputcin;assign(cout,sum}=a+b+cin;endmodule【例11】行为描述的4位全加器moduleadd4_3(cout,sum,a,bzcin);output[3:0]sum;outputcout;input[3:0]a,b;inp
11、utcin;reg[3:0]sum;regcout;always@(aorborcin)begin{cout,sum}=a+b+cin;endendmodule【例12】非流水线方式8位全加器moduleadder8(cout,sum,inazinb,cin,elk);output[7:0]sum;outputcout;input[7:0]ina,inb;inputcin,elk;reg[7:0]tempa,tempb,sum;regcout;regtempc;always@(po
