计算机组成原理实验_乘法器

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1、学院计算机组成原理实验报告 年级　　学号　姓名　成绩　　专业　实验地点　指导教师　　　实验项目乘法器　　实验日期　一．实验目的：理解并掌握乘法器的原理二．实验步骤（1）打开QuartusII。（2）将子板上的JTAG端口与PC机的并行口用下载电缆连接。打开实验台电源。（3）执行Tools—Programmer命令，将shifter.sof下载到FPGA中。注意在执行Programmer命令中应在Programmer/configure下的方框中打勾，然后下载。（4）在实验台上通过模式开关选择FPGA-CPU独立调试模式010.（5）将短路子DZ3短接且短路子DZ4断路。使FPGA-C

2、PU所需要的时钟使用正单脉冲时钟。三．实验代码--实验6.6Booth乘法器LIBRARYIEEE;USEIEEE.Std_logic_1164.ALL;ENTITYbooth_multiplierISGENERIC(k:POSITIVE:=3);--inputnumberwordlengthlessonePORT(multiplicand:INBIT_VECTOR(kDOWNTO0);multiplier:INBIT_VECTOR(kDOWNTO0);clock:INBIT;product:INOUTBIT_VECTOR((2*k+2)DOWNTO0);final:OUTBIT);

3、ENDbooth_multiplier;ARCHITECTUREstructuralOFbooth_multiplierISSIGNALmdreg:BIT_VECTOR(kDOWNTO0);SIGNALadderout:BIT_VECTOR(kDOWNTO0);SIGNALcarries:BIT_VECTOR(kDOWNTO0);SIGNALaugend:BIT_VECTOR(kDOWNTO0);SIGNALtcbuffout:BIT_VECTOR(kDOWNTO0);SIGNALadder_ovfl:BIT;SIGNALcomp:BIT;SIGNALclr_md:BIT;SIGNA

4、Lload_md:BIT;SIGNALclr_pp:BIT;SIGNALload_pp:BIT;SIGNALshift_pp:BIT;SIGNALboostate:NATURALRANGE0TO2*(k+1):=0;BEGINPROCESS--mainclockedprocesscontainingallsequentialelementsBEGINWAITUNTIL(clock'EVENTANDclock='1');--registertoholdmultiplicandduringmultiplicationIFclr_md='1'THENmdreg<=(OTHERS=>'0')

5、;ELSIFload_md='1'THENmdreg<=multiplicand;ELSEmdreg<=mdreg;ENDIF;--register/shifteraccumulatespartialproductvaluesIFclr_pp='1'THENproduct<=(OTHERS=>'0');product((k+1)downto1)<=multiplier;ELSIFload_pp='1'THENproduct((2*k+2)DOWNTO(k+2))<=adderout;--addtotophalfproduct((k+1)DOWNTO0)<=product((k+1)D

6、OWNTO0);--refreshbootmhalfELSIFshift_pp='1'THENproduct<=productSRA1;--shiftrightwithsignextendELSEproduct<=product;ENDIF;ENDPROCESS;--adderadds/subtractspartialproducttomultiplicandaugend<=product((2*k+2)DOWNTO(k+2));addgen:FORiINadderout'RANGEGENERATElsadder:IFi=0GENERATEadderout(i)<=tcbuffout

7、(i)XORaugend(i)XORproduct(1);carries(i)<=(tcbuffout(i)ANDaugend(i))OR(tcbuffout(i)ANDproduct(1))OR(product(1)ANDaugend(i));ENDGENERATE;otheradder:IFi/=0GENERATEadderout(i)<=tcbuffout(i)XORaugend(i)XORcarries(i-1);carries(i)<=(tcbu