斯巴达克思一古罗马的流血大角

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1、Chapter5TheLC-3InstructionSetArchitectureISAOverviewOperateinstructionsDataMovementinstructionsControlInstructionsLC-3datapathLC-3ISAOverviewMemoryorganizationAddressspace:216=64klocationsAddressability:WordWordsize=2bytes=>totalmemory=64kx2=128kbytesRegisters8x16bitGeneralPurposeRegisters:R

2、0-R73x1bitConditionCodeRegisters:N,Z,PSomespecialpurposeregisters(morelater)Instructions16bitinstructions,with4bitopcodesNativeDataType:only2’scomplementintegerAddressingModes:Immediate,Register,Direct,Indirect&Base+Offset2LC-3InstructionsOperateManipulatedatadirectly-arithmeticorbitwiselogi

3、cADD,AND,NOTDataMovementMovedatabetweenmemoryandregistersLD,LDI,LDR,LEA,ST,STI,STRControlChangethesequenceofinstructionexecutionBR,JMP/RET,JSR/JSSR,TRAP,RTI3InstructionConstructionTwomainpartsOpcode:specifieswhattheinstructiondoes.Operand(s):whattheinstructionactson.Instructionsetscanbecompl

4、exorsimple(CISC,RISC),single-wordormulti-word.LC-3Singleword(16bit)instructions.4-bitopcode=>16instructions(verysimpleset!)remaining12bitsspecifyoperand(s),accordingtotheaddressingmodepropertoeachinstruction.4LC3InstructionsLC-3Instructionword:16bitsOpcodeIR[15:12]:4bitsallow16instructionssp

5、ecifiestheinstructiontobeexecutedOperandsIR[11:0]containsspecificationsfor:Immediatevalue:5bitsRegisters:8GPRs(i.e.require3bitsforaddressing)AddressGenerationbits:Offset(11or9or6bits)(morelater)ExamplesADDDR,SR1,SR2;DR(SR1)+(SR2)[15:12][11:9][8:6][2:0]LDRDR,BaseR,Offset;DRMem[BaseR+Offset]

6、[15:12][11:9][8:6][5:0]5AddressingModesNote:theeffectiveaddress(ea)isthememorylocationoftheoperandTheLC-3supportsfiveaddressingmodes:theoperandislocated:intheinstructionitself(immediate)inaregisterinmemory:theeaisencodedintheinstruction(direct,orPC-relative)apointertotheeaisencodedintheinstr

7、uction(indirect)apointertotheeaisstoredinaregister(relative,orbase+offset)6OperateInstructionsNOT(unaryoperator)destinationregisterinIR[11:9]andasinglesourceregisterinIR[8:6].bitsIR[5:0]areall1s.ADD&AND(binaryoperators)destinationregisterinIR[11:9]