26-parallelism

《26-parallelism》由会员上传分享，免费在线阅读，更多相关内容在学术论文-天天文库。

1、CarnegieMellonThread-LevelParallelism15-213/18-213:IntroductiontoComputerSystems26thLecture,April21,2015Instructors:SethCopenGoldstein,FranzFranchetti,RalfBrown,andBrianRailing1CarnegieMellonTodayParallelComputingHardwareMulticoreMultipleseparateprocessorsonsinglechipHowtheymaintainconsistentvi

2、ewofmemoryHyperthreadingEfficientexecutionofmultiplethreadsonsinglecoreThread-LevelParallelismSplittingprogramintoindependenttasksExample:ParallelsummationSomeperformanceartifactsDivide-andconquerparallelismExample:Parallelquicksort2CarnegieMellonMulticoreProcessorCore0Coren-1RegsRegsL1L1L1

3、L1d-cachei-cache…d-cachei-cacheL2unifiedcacheL2unifiedcacheL3unifiedcache(sharedbyallcores)MainmemoryIntelNehalemProcessorE.g.,Sharkmachines(8cores/machine)Multipleprocessorsoperatingwithcoherentviewofmemory3CarnegieMellonMemoryConsistencyinta=1;intb=100;Thread1:Thread2:Wa:a=2;Wb:b=200;Rb:print(

4、b);Ra:print(a);Whatarethepossiblevaluesprinted?DependsonmemoryconsistencymodelAbstractmodelofhowhardwarehandlesconcurrentaccesses4CarnegieMellonNon-CoherentCacheScenariointa=1;Write-backcaches,withoutintb=100;coordinationbetweenthemThread1:Thread2:Wa:a=2;Wb:b=200;Rb:print(b);Ra:print(a);Thread1

5、CacheThread2Cachea:2b:100a:1b:200print1print100MainMemorya:1b:1005CarnegieMellonMemoryConsistencyinta=1;intb=100;ThreadconsistencyconstraintsWaRbThread1:Thread2:Wa:a=2;Wb:b=200;WbRaRb:print(b);Ra:print(a);Whatarethepossiblevaluesprinted?DependsonmemoryconsistencymodelAbstractmodelofhowhardwareha

6、ndlesconcurrentaccesses6CarnegieMellonMemoryConsistencyinta=1;intb=100;ThreadconsistencyconstraintsWaRbThread1:Thread2:Wa:a=2;Wb:b=200;WbRaRb:print(b);Ra:print(a);Whatarethepossiblevaluesprinted?DependsonmemoryconsistencymodelAbstractmodelofhowhardwarehandlesconcurrentaccessesSequentialconsiste

7、ncyOveralleffectconsistentwitheachindividualthreadOtherwise,arbitraryinterleaving7CarnegieMellonSequentialConsistencyExampleThreadconsistencyinta=1;constraintsintb=100;WaRbWbRaThread1:Thread2:Wa:a=2;Wb:b=