11-memory-hierarchy

11-memory-hierarchy

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时间:2019-07-29

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1、WuhanUniversityTheMemoryHierarchyComputerSystem11thLecture,May16,2017Instructor:CienFan1WuhanUniversityTodayStoragetechnologiesandtrendsLocalityofreferenceCachinginthememoryhierarchy2WuhanUniversityRandom-AccessMemory(RAM)KeyfeaturesRAMistraditionallypackagedasachip.Basicstor

2、ageunitisnormallyacell(onebitpercell).MultipleRAMchipsformamemory.RAMcomesintwovarieties:SRAM(StaticRAM)DRAM(DynamicRAM)3WuhanUniversitySRAMvsDRAMSummaryTrans.AccessNeedsNeedsperbittimerefresh?EDC?CostApplicationsSRAM4or61XNoMaybe100xCachememoriesDRAM110XYesYes1XMainmemories,fr

3、amebuffers4WuhanUniversityNonvolatileMemoriesDRAMandSRAMarevolatilememoriesLoseinformationifpoweredoff.NonvolatilememoriesretainvalueevenifpoweredoffRead-onlymemory(ROM):programmedduringproductionProgrammableROM(PROM):canbeprogrammedonceEraseablePROM(EPROM):canbebulkerased(UV

4、,X-Ray)ElectricallyeraseablePROM(EEPROM):electronicerasecapabilityFlashmemory:EEPROMs.withpartial(block-level)erasecapabilityWearsoutafterabout100,000erasingsUsesforNonvolatileMemoriesFirmwareprogramsstoredinaROM(BIOS,controllersfordisks,networkcards,graphicsaccelerators,secur

5、itysubsystems,…)Solidstatedisks(replacerotatingdisksinthumbdrives,smartphones,mp3players,tablets,laptops,…)Diskcaches5WuhanUniversityTraditionalBusStructureConnectingCPUandMemoryAbusisacollectionofparallelwiresthatcarryaddress,data,andcontrolsignals.Busesaretypicallysharedbymul

6、tipledevices.CPUchipRegisterfileALUSystembusMemorybusI/OMainBusinterfacebridgememory6WuhanUniversityMemoryReadTransaction(1)CPUplacesaddressAonthememorybus.RegisterfileLoadoperation:movqA,%raxALU%raxMainmemoryI/Obridge0ABusinterfacexA7WuhanUniversityMemoryReadTransaction(2)Mainme

7、moryreadsAfromthememorybus,retrieveswordx,andplacesitonthebus.RegisterfileLoadoperation:movqA,%raxALU%raxMainmemoryI/Obridgex0BusinterfacexA8WuhanUniversityMemoryReadTransaction(3)CPUreadwordxfromthebusandcopiesitintoregister%rax.RegisterfileLoadoperation:movqA,%raxALU%raxxMainmem

8、oryI/Obridge0Businterfacex

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