超大CMOS集成电路原理chapter10

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1、DigitalIntegratedCircuitsADesignPerspectiveTimingIssuesJanM.RabaeyAnanthaChandrakasanBorivojeNikolićJanuary20031SynchronousTiming2TimingDefinitions3LatchParametersDClkQDQClktc-qtholdPWmtsutd-qDelayscanbedifferentforrisingandfallingdatatransitionsT4RegisterParametersDCl

2、kQDQClktc-qtholdTtsuDelayscanbedifferentforrisingandfallingdatatransitions5ClockUncertaintiesSourcesofclockuncertainty6ClockNonidealitiesClockskewSpatialvariationintemporallyequivalentclockedges;deterministic+random,tSKClockjitterTemporalvariationsinconsecutiveedgesoft

3、heclocksignal;modulation+randomnoiseCycle-to-cycle(short-term)tJSLongtermtJLVariationofthepulsewidthImportantforlevelsensitiveclocking7ClockSkewandJitterBothskewandjitteraffecttheeffectivecycletimeOnlyskewaffectstheracemarginClkClktSKtJS8ClockSkew#ofregistersClkdelayIn

4、sertiondelayMaxClkskewEarliestoccurrenceofClkedgeNominal–/2LatestoccurrenceofClkedgeNominal+/29PositiveandNegativeSkew10PositiveSkewLaunchingedgearrivesbeforethereceivingedge11NegativeSkewReceivingedgearrivesbeforethelaunchingedge12TimingConstraintsMinimumcycletim

5、e:T-=tc-q+tsu+tlogicWorstcaseiswhenreceivingedgearrivesearly(positive)13TimingConstraintsHoldtimeconstraint:t(c-q,cd)+t(logic,cd)>thold+WorstcaseiswhenreceivingedgearriveslateRacebetweendataandclock14ImpactofJitter15LongestLogicPathinEdge-TriggeredSystemsClkTTSUTC

6、lk-QTLMLatestpointoflaunchingEarliestarrivalofnextcycleTJI+d16ClockConstraintsinEdge-TriggeredSystemsIflaunchingedgeislateandreceivingedgeisearly,thedatawillnotbetoolateif:MinimumcycletimeisdeterminedbythemaximumdelaysthroughthelogicTc-q+TLM+TSU

7、TLM+TSU+d+2TJI

8、I,1