Tues1030 RISC-V External Debug

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1、RISC-VExternalDebug(akaJTAGdebugging)TimNewsomeSiFiveGoals●Debugsystemthatworksforeverybody○Givefeedback!●WorkingsystemdonebyJuly1,2016○RISC-VonanFPGA○HardwareJTAGdebugger●SpecificationwillbesubmittedtotheRISC-VFoundation●OpenSourcereleaseofdebugger●OpenSource

2、releaseofimplementationsforRocketChipandZ-ScaleStatus●SpecificationismostlycompleteFeatures●Performreads/writesonthesystembus●Frameworktodebuganycomponentintheplatform(halt/freeze/run/step)●Softwarebreakpoints.●AccessRISC-Vregisters.●ExecutearbitraryinstructionsonahaltedRISC-

3、Vcore.●Usedifferentdebugtransports.(OnlyJTAGisspecified,1149.7coming.)●Usedebugtransportforsomethingelse(eg.serialport).●Debugcodefromveryfirstinstructionexecuted.●Hardwarebreakpoints/tracetriggers.●Tracecoreexecutiontoon-oroff-chipRAM.(Maynotbeimplemented.)debugger(gdb,…)Ove

4、rviewDebugTransport(JTAG,USB,…)PlatformDebugTransportModuleSystemBusDebugProgramROM+RAMDebugModuleTraceModuleComponComponHardwareBreakpointentModuleComponententRISC-VcoreDebugTransportModule●ProvidesaccesstotheSystemBus●Implementsamessagequeue●OptionalauthenticationGenericCom

5、ponentDebugging●Abstract○freeze○halt○step○run●Maysendmessagesthroughmessagequeue●OptionalauthenticationRISC-VControlandStatusRegisters●CSRsareexposedontheSystemBus●NewCSRs:○DebugControlandStatus(dcsr)○DebugPC(dpc)○DebugMailbox0(dmbox0)○DebugMailbox1(dmbox1)○DebugState(dstate)

6、○PCSample(pcsample)●Busaccessestodmbox[01]setbitsindstateDebugMemory●AccessiblethroughSystemBus●Notcached●SharedbetweenallcoresROM1KB,butmorethan50%nops.“functions”:●entry●exit●send_x8●receive_x8●instruction_loopRAMAtleast8bytes.16bytesrecommended.Halt1.Core3.Corea.SavesPCtoD

7、ebugPCa.Seesthatmbox0wasreadb.JumpstoDebugROMb.JumpstoDebugRAMi.Writesx1tombox0c.Jumpstoinstruction_loopii.Writesx9tombox1d.Writesx8tombox0iii.Signalsdebuggere.Signalsdebuggeriv.Waitsforreadtombox0f.Waitsforwritetombox02.Debugger4.Debuggera.Noticesmessageorpollsdstatea.Notice

8、smessageorpollsdstateb.ReadsPCfromDebugPCb.Readsx8frommbox0c.Readsx9