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ID:40101744
大小:441.03 KB
页数:134页
时间:2019-07-21
《Skew-Tolerant Circuit Design》由会员上传分享,免费在线阅读,更多相关内容在学术论文-天天文库。
1、SKEW-TOLERANTCIRCUITDESIGNADISSERTATIONSUBMITTEDTOTHEDEPARTMENTOFELECTRICALENGINEERINGANDTHECOMMITTEEONGRADUATESTUDIESOFSTANFORDUNIVERSITYINPARTIALFULFILLMENTOFTHEREQUIREMENTSFORTHEDEGREEOFDOCTOROFPHILOSOPHYDavidHarrisFebruary1999(c)Copyright1999byDavidHarris
2、AllRightsReservediiIcertifythatIhavereadthisdissertationandthatinmyopinionitisfullyadequate,inscopeandquality,asadissertationforthedegreeofDoctorofPhilosophy._________________________________MarkHorowitz,PrincipalAdvisorIcertifythatIhavereadthisdissertationan
3、dthatinmyopinionitisfullyadequate,inscopeandquality,asadissertationforthedegreeofDoctorofPhilosophy._________________________________BruceWooleyIcertifythatIhavereadthisdissertationandthatinmyopinionitisfullyadequate,inscopeandquality,asadissertationforthedeg
4、reeofDoctorofPhilosophy._________________________________AbbasEl-GamalApprovedfortheUniversityCommitteeonGraduateStudies:_________________________________iiiAbstractAscycletimesinhigh-performancedigitalsystemsshrinkfasterthansimpleprocessimprovementallows,seq
5、uencingoverheadconsumesanincreasingfractionoftheclockperiod.Inparticular,theoverheadoftraditionaldominopipelinescanconsume25%ormoreofthecycletimeinaggressivesystems.Fortunately,thedesignercanhidemuchofthisoverheadthroughbetterdesigntechniques.Thekeytoskew-tol
6、erantdesignisavoid-inghardedgesinwhichdatamustsetupbeforeaclockedgebutwillnotcontinuepropa-gatinguntilaftertheclockedge.Skew-tolerantdominocircuitsusemultipleoverlappingclockstoeliminatelatches,removinghardedgesandhidingthesequencingoverhead.Thisthesispresent
7、sasystematicapproachtoskew-tolerantcircuitdesign,combiningbothstaticanddominocircuits.Itdescribesthetradeoffsinclockingschemesandconcludesthatfourphasesisareasonabledesignchoicewhichcantoleratenearlyaquartercycleofskewandissimpletoimplement.Four-phaseskew-tol
8、erantdominointegrateseasilywithstaticlogicusingtransparentorpulsedlatchesandsharesaconsistentscanmethodologyprovidingtestabilityofallcyclesoflogic.Timingtypesaredefinedtohelpunderstandandv
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