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1、第8章有限状态机的设计VerilogHDL数字系统设计及仿真本章内容有限状态机的类型一段式、两段式和三段式状态机写法状态编码2有限状态机的类型moore型，也称为摩尔型mealy型，也称为米利型3moore型红绿灯状态转换图4模型代码moduletrafficlight1(clock,reset,red,yellow,green);inputclock,reset;//输入时钟和复位信号outputred,yellow,green;//输出红黄绿的驱动信号regred,yellow,green;reg[1:0]current_s
2、tate,next_state;//保存当前状态和下一状态parameterred_state=2'b00,yellow_state=2'b01,green_state=2'b10,delay_r2y=4'd8,delay_y2g=4'd3,delay_g2r=4'd11;//参数声明5//第一段always，用于把下一状态赋值给当前状态always@(posedgeclockorposedgereset)beginif(reset)current_state<=red_state;elsecurrent_state<=next
3、_state;end6//第二段always，用于根据当前状态判断下一状态，并产生输出always@(current_state)begincase(current_state)red_state:beginred=1;yellow=0;green=0;repeat(delay_r2y)@(posedgeclock);next_state=yellow_state;end7完成状态描述yellow_state:beginred=0;yellow=1;green=0;repeat(delay_y2g)@(posedgeclock)
4、;next_state=green_state;endgreen_state:beginred=0;yellow=0;green=1;repeat(delay_g2r)@(posedgeclock);next_state=red_state;enddefault:beginred=1;yellow=0;green=0;next_state=red_state;endendcaseendendmodule8测试信号initialclock=0;always#10clock=~clock;initialbeginreset=1;#1
5、reset=0;//产生一个复位信号沿#10000reset=1;//主要工作时间#20$stop;end9功能仿真时序仿真10增加一个可变计数器always@(posedgeclockorposedgereset)beginif(reset)light_count<=0;elseif(light_count==light_delay)//达到规定的计数值light_delay时置1light_count<=1;elselight_count<=light_count+1;end11case(current_state)red_
6、state:beginred=1;yellow=0;green=0;light_delay=red_delay;if(light_count==light_delay)next_state=yellow_state;endyellow_state:beginred=0;yellow=1;green=0;light_delay=yellow_delay;if(light_count==light_delay)next_state=green_state;end12green_state:beginred=0;yellow=0;gr
7、een=1;light_delay=green_delay;//延迟时间被赋值为green时的延迟if(light_count==light_delay)//达到延迟时间变为下一状态next_state=red_state;end13mealy型红绿灯状态转换图14设计模块moduletrafficlight3(clock,reset,x,red,yellow,green);inputclock,reset;inputx;//多添加了一个输入端xoutputred,yellow,green;regred,yellow,green
8、;reg[1:0]current_state,next_state;parameterred_state=2'b00,yellow_state=2'b01,green_state=2'b10,delay_r2y=4'd8,delay_y2g=4'd3,delay
