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1、IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.39,NO.3,MARCH2004463A500-MHz–1.25-GHzFast-LockingPulsewidthControlLoopWithPresettableDutyCycleSung-RungHan,StudentMember,IEEE,andShen-IuanLiu,SeniorMember,IEEEAbstract—A500-MHz–1.25-GHzfast-lockingpulsewidthcon-Thispaperproposesusing
2、anewapproachtoachieveafast-trolloop(PWCL)withpresettabledutycycleisrealizedin0.35-mlockingandduty-cycle-presettablePWCL.TheoperationoftheCMOStechnology.Theproposedvoltage-difference-to-digitalcon-circuitisinvestigatedinSectionIIwherenewcircuitmodelsandverterandswitchedc
3、hargepumpcircuitsreducethelocktimeofdesignequationsaredeveloped.Thedesignapproachforafast-aconventionalPWCL.ComparedwiththeconventionalPWCL,theproposedcircuitcanreducethelocktimebyafactorof2.58.AlockingPWCLisdescribedinSectionIII.SectionIVdiscussesmethodtopresetthedutyc
4、ycleoftheoutputclockisalsodescribed.thedesignissuesofduty-cyclesetting.TheexperimentalresultsCircuitmeasurementsverifythatthedutycycleoftheoutputclockareillustratedinSectionV.Finally,conclusionsarepresentedincanbeadjustedfrom35%to70%instepsof5%.SectionVI.IndexTerms—Duty
5、-cyclepresetting,fastlocking,pulsewidthcontrolloop(PWCL),switchedchargepump,voltage-differ-II.TRANSIENTANALYSISOFTHECONVENTIONALPWCLence-to-digitalconverter.TheconventionalPWCL[6]isshowninFig.1(a).Inordertodesignafast-lockingPWCL,thetransientmechanismmustI.INTRODUCTIONb
6、einvestigated.Tosimplifyanalysis,isinitializedtoOMEETthedemandforhigh-speedoperationtoday,andisinitializedtoitsequilibriumvoltage,.BasedonTmanysystemsadoptadoubledatarate(DDR)technology,thiscondition,thetransientresponseofthecontrolvoltagesuchasDDRSDRAManddouble-samplin
7、gADC.InthesecanbesketchedinFig.1(b).Asshowninthefigure,therearesystems,bothrisingandfallingedgesoftheclockareusedtofourregionsinthetransient.Thebehaviorofeachregioncanbesampletheinputdata,requiringthatthedutycycleoftheclockdescribedasfollows.bepreciselymaintainedat50%.T
8、herefore,howtogenerateaclockwithprecise50%dutycycleforhigh-speedoperationA.NonlinearRegionisanimportantissue.S
