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1、ORION2.0:AFastandAccurateNoCPowerandAreaModelforEarly-StageDesignSpaceExplorationAndrewB.Kahng‡†,BinLi+,Li-ShiuanPeh+andKambizSamadi†‡CSEand†ECEDepartments,UniversityofCalifornia,SanDiego,LaJolla,CA+EEDepartment,PrincetonUniversity,Princeton,NJEmail:fabk,ksamadig@ucsd.edu,fbinl,
2、pehg@princeton.eduAbstractcircuitimplementation&floorplanAsindustrymovestowardsmany-corechips,networks-on-chipbufferingscheme•locationofallroutersin(NoCs)areemergingasthescalablefabricforinterconnectingthedesign•SRAM/registerFIFOthecores.Withpowernowthefirst-orderdesignconstraint
3、,early-•MUX/treecrossbarstageestimationofNoCpowerhasbecomecruciallyimportant.Area•differentarbitrationschemeORION[29]wasamongstthefirstNoCpowermodelsreleased,•hybridbufferingschemeFIFOandhassincebeenfairlywidelyusedforearly-stagepoweres-ArbiterLeakagetimationofNoCs.However,whenva
4、lidatedagainstrecentNoCarchitecturalparametersCrossbarprototypes–theIntel80-coreTeraflopschipandtheIntelScal-•#ofports;#ofbuffersClockableCommunicationsCore(SCC)chip–wesawsignificantde-•#ofxbarports;#ofVCLinkDynamicviationthatcanleadtoerroneousNoCdesignchoices.This•voltage,frequen
5、cyORIONModelpromptedourdevelopmentofORION2.0,anextensiveenhance-mentoftheoriginalORIONmodelswhichincludescompletelytechnologyparametersnewsubcomponentpowermodels,areamodels,aswellasim-InterconnectDevicesAutomaticprovedandupdatedtechnologymodels.ValidationagainsttheT.libBuildingB
6、locksExtractiontwoIntelchipsconfirmsasubstantialimprovementinaccuracyINVX1HILDAutomaticovertheoriginalORION.Acasestudywiththesepowermod-LEF/ITFNOR2x1WminExtractionelspluggedwithintheCOSI-OCCNoCdesignspaceexplorationSInterconnectMASTARNAND2x1tool[23]confirmstheneedfor,andvalueof,ac
7、curateearly-stageminITRSR0ChapterdILDNoCpowerestimation.ToensurethelongevityofORION2.0,TIERS(L,I,SG,G)SPICESim.Cinwewillbereleasingitwrappedwithinasemi-automatedflowthatPTMIoffautomaticallyupdatesitsmodelsasnewtechnologyfilesbecomeLocalGlobalavailable.IntermediateSemi-global1Intro
8、ductionFigure1:ORION2.0modelingmethodology.Powe
