锁相频率合成器论文-论文

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1、锁相频率合成器论文-论文锁相频率合成器论文目  录 技术要求………………………………………………………………………3定时特征………………………………………………………………………6绝对最大额定值………………………………………………………………6引脚配置与函数描述…………………………………………………………8典型性能品质特性曲线……………………………………………………10概述…………………………………………………………………………12   基准输入部分…………………………………………………………12   射频输入级……………………………………………………………13寄存器图………

2、……………………………………………………………17FRAC／INT寄存器(R0)………………………………………………18MOD／R寄存器(R1)……………………………………………………19相位寄存器(R2)………………………………………………………21函数寄存器(R3)………………………………………………………21充电泵寄存器(R4)……………………………………………………22下电寄存器(R5)………………………………………………………23   多路寄存器(R6)………………………………………………………24设计…………………………………………………………………………24  

3、 工作例子………………………………………………………………25   分支机构………………………………………………………………25   上电初始化……………………………………………………………26   改变锁相环的频率和相位检查表……………………………………27应用…………………………………………………………………………28   GSM本机振荡器………………………………………………………28   连接电路………………………………………………………………30   对集成电路芯片比例封装组件PCB设计方针………………………31外部尺寸………………………………………………………………

4、……32   命令指令………………………………………………………………32Abstract：TheADF4193frequencysynthesizercanbeusedtoimplementlocaloscillatorsintheupconversionanddownconversionsectionsofwirelessreceiversandtransmitters.ItsarchitectureisspecificallydesignedtomeettheGSM/EDGElocktimerequirementsforbasestations.Itconsistsof

5、alownoise,digitalphasefrequencydetector(PFD),andaprecisiondifferentialchargepump.Thereisalsoadifferentialamplifiertoconvertthedifferentialchargepumpoutputtoasingleendedvoltagefortheexternalvoltagecontrolledoscillator(VCO).TheΣ-Δbasedfractionalinterpolator,workingwiththeNdivider,allowprogram

6、mablemodulusfractional-Ndivision.Additionally,the4-bitreference(R)counterandon-chipfrequencydouberallowsselectablereferencesignal(REFIN)frequenciesatthePFDinput.Acompletephase-lockedloop(PLL)canbeimplementedifthesynthesizerisusedwithanexternalloopfilterandaVCO.Theswitchingarchitectureensure

7、sthatthePLLsettlesinsidetheGSMtimeslotguardperiod,removingtheneedforasecondPLLandassociatedisolationswitches.Thisdecreasescost,complexity,PCBarea,shielding,andcharacterizationonpreviousping-pongGSMPLLarchitectures.摘要:ADF4193频率合成器可用于实现本机振荡在上变频和下变频部分的无线电接收