实验五实验报告

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1、实验五、有限状态机的硬件描述语言设计方法一、实验程序libraryieee;useieee.std_logic_1164.all;entityztjisport(clk,din,clr:instd_logic;ab:outstd_logic_vector(3downto0));endztj;architectureoneofztjistypestateis(st0,st1,st2,st3,st4,st5,st6,st7,st8);signald:std_logic_vector(7downto0);signalcurrent_state,next

2、_state:state;begind<="11100101";reg:process(clk,clr)beginifclr='1'thencurrent_state<=st0;elsifclk='1'andclk'eventthencurrent_state<=next_state;endif;endprocess;com:process(current_state,din)begincasecurrent_stateiswhenst0=>ifdin=d(7)thennext_state<=st1;elsenext_state<=st0;end

3、if;ab<="1011";whenst1=>ifdin=d(6)thennext_state<=st2;elsenext_state<=st0;endif;ab<="1011";whenst2=>ifdin=d(5)thennext_state<=st3;elsenext_state<=st0;endif;ab<="1011";whenst3=>ifdin=d(4)thennext_state<=st4;elsenext_state<=st0;endif;ab<="1011";whenst4=>ifdin=d(3)thennext_state<

4、=st5;elsenext_state<=st0;endif;ab<="1011";whenst5=>ifdin=d(2)thennext_state<=st6;elsenext_state<=st0;endif;ab<="1011";whenst6=>ifdin=d(1)thennext_state<=st7;elsenext_state<=st0;endif;ab<="1011";whenst7=>ifdin=d(0)thennext_state<=st8;elsenext_state<=st0;endif;ab<="1011";whenst

5、8=>next_state<=st0;ab<="1010";whenothers=>next_state<=st0;ab<="1011";endcase;endprocess;endone;仿真测试波形引脚配置