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1、Thisisthefirstofamulti-partseries,tointroduceFinFETtechnologytoSemiWikireaders.Thesearticleswillhighlightthetechnology'skeycharacteristics,anddescribesomeoftheadvantages,disadvantages,andchallengesassociatedwiththistransition.TopicsinthisserieswillincludeFinFETfabrication,modeling,
2、andtheresultingimpactuponexistingEDAtoolsandflows.(And,ofcourse,feedbackfromSemiWikireaderswillcertainlyhelpinfluencesubsequenttopics,aswell.)ScalingofplanarFET'shascontinuedtoprovideperformance,power,andcircuitdensityimprovements,uptothe22/20nmprocessnode.AlthoughactiveresearchonF
3、inFETdeviceshasbeenongoingformorethanadecade,theirusebyaproductionfabhasonlyrecentlygainedadoption.Thebasiccross-sectionofasingleFinFETisshowninFigure1.Thekeydimensionalparametersaretheheightandthicknessofthefin.Aswithplanardevices,thedrawngatelength(notshown)separatingthesourceand
4、drainnodesisa“criticaldesigndimension”.Aswillbedescribedinthenextinstallmentinthisseries,theh_finandt_finmeasuresaredefinedbythefabricationprocess,andarenotdesignparameters.Figure1.FinFETcross-section,withgatedielectriconfinsidewallsandtop,andbulksiliconsubstrateTheFinFETcross-sect
5、iondepictsthegatespanningbothsidesandthetopofthefin.Forsimplicity,asinglegatedielectriclayerisshown,abstractingthecomplexmulti-layerdielectricsusedtorealizean“effective”oxidethickness(EOT).Similarly,asimplegatelayerisshown,abstractingthemultiplematerialscomprisingthe(metal)gate.Int
6、heresearchliterature,FinFET'shavealsobeenfabricatedwithathickdielectriclayerontop,limitingthegate'selectrostaticcontrolonthefinsilicontojustthesidewalls.Someresearchershaveevenfabricatedindependentgatesignals,oneforeachfinsidewall–inthiscase,onegateisthedeviceinputandtheotherprovid
7、estheequivalentofFET“backbias”control.Fortheremainderofthisseries,thediscussionwillfocusonthegateconfigurationshown,withathingatedielectriconthreesides.(Inteldenotesthisas“Tri-Gate”intheirrecentIvyBridgeproductannouncements.)Duetothemorecomplexfabricationsteps(andcosts)of“dual-gate
8、”and“independent-gate”devi
