资源描述：
《(内存基本知识)4DRAM工作原理》由会员上传分享，免费在线阅读，更多相关内容在教育资源-天天文库。
1、DRAM工作原理DynamicRandomAccessMemoryEachcellisacapacitor+atransistorVerysmallsizeSRAMusessixtransistorspercellDividedintobanks,rows&columnsEachbankcanbeindependentlycontrolledDRAMMainMemoryEverythingthathappensinthecomputerisresidentinmainmemoryCapacity:around100Mbyteto100GbyteRandomaccessTypicalacc
2、esstimeis10-100nanosecondsWhyDRAMforMainMemory???Costeffective(smallchipareathanSRAM)?HighSpeed(thanHDD,flash)?HighDensity(~Gbyte)?MassProduction……MainmemoryNotation:K,M,G?Instandardscientificnomenclature,themetricmodifiersK,M,andGtorefertofactorsof1,000,1,000,000and1,000,000,000respectively.?Com
3、puterengineershaveadoptedKasthesymbolforafactorof1,024(210)?K:1,024(210)?M:1,048,576(220)?G:1,073,741,824(230)?DRAM’density?256M-bit?512M-bitDRAMDensityWhatisaDRAM??DRAMstandsforDynamicRandomAccessMemory.?RandomaccessreferstotheabilitytoaccessanyoftheinformationwithintheDRAMinrandomorder.?Dynamic
4、referstotemporaryortransientdatastorage.Datastoredindynamicmemoriesnaturallydecaysovertime.Therefore,DRAMneedperiodicrefreshoperationtopreventdataloss.Memory:DRAMposition?Semiconductormemorydevice?ROM:Nonvolatile?MaskROM?EPROM?EEPROM?Flash?NAND:lowspeed,highdensity?NOR:highspeed,lowdensity?RAM:Vo
5、latile?DRAM:DynamicRandomAccessMemory?SRAM:StaticRandomAccessMemory?PseudoSRAMDRAMTrend:Future?HighSpeed-DDR(333MHz~500MHz),DDR2(533~800Mbps),DDR3(800~1600Mbps)-Skew-delayminimizedcircuit/logic:post-chargelogic,wave-pipelining-NewArchitecture:multi-bankstructure,highspeedInterface?LowPower-5.5V=>
6、3.3V(sdr)=>2.5V(ddr)=>1.8V(ddr2)=>1.5v(ddr3)=>1.2v?-SmallvoltageswingI/Ointerface:LVTTLtoSSTL,opendrain-LowPowerDRAM(PASR,TCSR,DPD)?HighDensity-Memorydensity:32MB=>64MB=>.....1GB=>2GB=>4GB-applicationexpansion:mobile,memoryDBforshock(thanHDD)-Processshrink:145nm(‘03)=>120nm(‘04)=>100nm=>90nm=>80n
7、m…?OtherTrends-CostEffectiveness,TechnicalCompatibility,Stability,Environment.ReliabilityStaticRAMSRAMBasicstorageelementisa4or6transistorcircuitwhichwillholda1or0aslongasthesystemcontinuestoreceivepowerNoneedforaperio
