Signed Arithmetic in Verilog 2001英文文献资料

Signed Arithmetic in Verilog 2001英文文献资料

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1、SignedArithmeticinVerilog2001–OpportunitiesandHazardsDr.GregTumbush,StarkeyLabs,ColoradoSprings,COIntroductionSignedDataTypesStarkeyLabsisinthebusinessofdesigningandTable1demonstratestheconversionofadecimalvaluetomanufacturinghearingaids.Thenewdigitalhearingsaidsasigned3

2、-bitvaluein2’scomplementformat.A3-bitsignedwedesignattheStarkeyLabsColoradoICDesignCentervaluewouldbedeclaredusingVerilog2001assigned[2:0]utilizeverycomplexDSPalgorithmsimplementedinbothA;.softwareandhardwareaccelerators.Thepredominantdatatypeusedinthesealgorithmsissigne

3、d.TheformatoftheDecimalValueSignedRepresentationsignedtypeistwo’scomplement.Thedesignationofsigned33’b011andtwo’scomplementisusedinterchangeablythroughout23’b010thisdocument.13’b001Verilog2001providesaveryrichsetofnewsigned03’b000datatypes.However,thereareissueswhenperfo

4、rming-13’b111operationssuchassignextension,truncationorrounding,-23’b110saturation,addition,andmultiplicationwithsignedvalues.-33’b101Thesenewdatatypes(intheory)freethedesignerfrom-43’b100worryingaboutsomeofthesesigneddatatypeissues.Morecompactandreadablecodeshouldresult

5、.However,intheTable1:Decimalto3-bitSignedspiritofVerilog,usageofthisnewfunctionalityis“userbeware”!ArithmeticmanipulationbetweenmixesofsignedTypeCastingandunsignedmaysimulateandsynthesizeinunintendedways.AssignmentsbetweendifferentlysizedtypesmayalsoThecastingoperators,$

6、unsignedand$signed,onlynotresultinwhatthedesignerintended.Doestheusageofhaveeffectwhencastingasmallerbitwidthtoalargerbit.signeddatatypesinarithmeticoperationsresultinsmallerorCastingusing$unsigned(signal_name)willzerofillthelargercircuits?input.ForexampleA=$unsigned(B)w

7、illzerofillBandVerilog1995providesonlyonesigneddatatype,assignittoA.Castingusing$signed(signal_name)willinteger.Theruleisthatifanyoperandinanexpressionissignextendtheinput.Forexample,A=$signed(B).Iftheunsignedtheoperationisconsideredtobeunsigned.ThesignbitisXorZthevaluew

8、illbesignextendedusingXorrulestillappliesforVerilog2001butnowallregs,wires,Z,respectively.Assigningtoas

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