Simultaneous Time Slack Budgeting and Retiming for Dual-Vdd FPGA Power Reduction

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1、SimultaneousTimeSlackBudgetingandRetimingforDual-VddFPGAPowerReductionYuHu1,YanLin1,LeiHe1andTimTuan21ElectricalEngineeringDept.,UCLA,LosAngeles,CA900952XilinxResearchLab.,2100LogicDr.,SanJose,CA95124ABSTRACTinterconnectstominimizepowerispresentedin[4,3].[3]isabletoreducemor

2、epowerthan[4],whereVddisdenedforaroutingtree.Fieldprogrammabledual-VddinterconnectsareeectivetoUniformwirelengthandbuffersizeisassumedin[3].However,reduceFPGApower.Assuminguniformlengthintercon-thestate•of•the•artcommercialFPGAshaveusedwiresegmentsofnects,existingworkhasdev

3、elopedtimeslackbudgetingtodifferentlengthstoimproveperformance[5].Becausethelowerminimizepowerbasedonestimatingthelowerboundofboundestimationofpowerreductionin[3]isnolongervalidforpowerreductionusingdual-Vddforgiventimeslack.Inthismixedlengthinterconnects,therstcontributiono

4、fthispaperispaper,weshowthatsuchlowerboundestimationcannottodevelopalinearprogramming(LP)basedslackbudgetingforbeextendedtomixedlengthinterconnectsthatareusedinmixed•lengthinterconnectsbasedonanupperboundestimationmodernFPGAs.Wedevelopatechniquetoestimatepowerofpowerreduction

5、.Theexperimentalresultsshow53%powerreductionusingdual-Vddformixedlengthinterconnects,reductiononaveragecomparedtosingle•Vddinterconnects.andapplylinearprogramming(LP)tosolveslackbudgetingTheslackbudgetingin[3]isappliedonlywithincombinationaltominimizepowerformixedlengthinterc

6、onnects.Exper-subcircuits.Simultaneouslyconsideringallcombinationalsubcir•imentsshow53%powerreductiononaveragecomparedtocuitsinasequentialcircuitmayreducemorepower,asillustratedsingle-Vddinterconnects.Furthermore,thispaperpresentsinFigure1,wherecircuitsin(a)and(b)havethesamec

7、lockperiodasimultaneousretimingandslackbudgetingalgorithmtoof4units.TochangeabufferfromVddHtoVddL,oneneedsareducepowerindual-VddFPGAsconsideringplacementslackof2units,noextrabuffercanbepoweredbyVddLin(a),and ip- opbindingconstraints.Thealgorithmisbasedonbutoneextrabuffercanbe

8、poweredbyVddLin(b).Because(b)mixedintegerandlinearprogramming(MILP)a