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1、CacheDesignforEmbeddedReal-TimeSystemsBruceJacobElectrical&ComputerEngineeringDepartmentUniversityofMarylandatCollegeParkblj@eng.umd.eduhttp://www.ee.umd.edu/~blj/ABSTRACTWhyisthisso?Theemphasisingeneral-purposesystemsistypicallyspeed,whichisrelatedtotheaverage
2、-casebehav-Cacheshavelongbeenamechanismforspeedingmemoryiorofasystem.Incontrast,real-timedesignersareconcernedaccessandarepopularinembeddedhardwarearchitectureswiththeaccuracyandreliabilityofasystem,whicharerelatedfrommicrocontrollerstocore-basedASICdesigns.How
3、ever,totheworst-casebehaviorofasystem.Whenareal-timesys-cachesareconsideredill-suitedforembeddedreal-timesys-temiscontrollingcriticalequipment,executiontimemustlietemsbecausetheyprovideaprobabilisticperformanceboost—withinpredesignedconstraints,withoutfail.Vari
4、abilityinexe-acachemayormaynotcontainthedesireddataatanygivencutiontimeiscompletelyunacceptablewhenthefunctionisamoment.Analysisthatguaranteeswhenanitemwillorwillcriticalcomponent,suchasintheflightcontrolsystemofannotbeinthecachehasprovendifficult,somanyreal-time
5、sys-airplaneortheantilockbrakesystemofanautomobile.temssimplydisablecachingandscheduletasksbasedonTheproblemwithusingtraditionalhardware-managedworst-casememoryaccesstime.cachesinreal-timesystemsisthattheyprovideaprobabilisticYetthereareseveralcacheorganization
6、sthatprovidetheperformanceboost;acachemayormaynotcontainthebenefitofcachingwithoutthereal-timedrawbacksofhard-desireddataatanygiventime.Ifthedataispresentintheware-managedcaches.Thesearesoftware-managedcaches,cache,accessisveryfast.Ifthedataisnotpresentinthecach
7、e,andseveraldifferentexamplescanbefound,fromDSP-styleaccessisveryslow.Typically,thefirsttimeamemoryitemison-chipRAMtoacademicdesigns.requested,itisnotinthecache.FurtheraccessestotheitemThispapercomparestheoperationandorganizationofarelikelytofindthedatainthecache
8、,thereforeaccesswillbecachesasfoundingeneral-purposeprocessors,microcontrol-fast.However,latermemoryrequeststootherlocationsmightlers,andDSPs;italsodiscussesdesignsforembedd
