分频器 计数器 数码管

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1、分频器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYdiv_50ISPORT(clk:INSTD_LOGIC;clear:INSTD_LOGIC;clk_out:OUTSTD_LOGIC);ENDdiv_50;ARCHITECTUREaOFdiv_50ISSIGNALtmp:INTEGERRANGE0TO49;BEGINp1:PROCESS(clear,clk)BEGINIFclear='0'THENtmp<=

2、0;ELSIFclk'eventANDclk='1'THENIFtmp=49THENtmp<=0;ELSEtmp<=tmp+1;ENDIF;ENDIF;ENDPROCESS;p2:PROCESS(tmp)BEGINIFclk'eventANDclk='1'THENIFtmp<25THENclk_out<='0';elseclk_out<='1';ENDIF;ENDIF;ENDPROCESSp2;ENDa;计数器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LO

3、GIC_UNSIGNED.ALL;ENTITYcount10ISPORT(clk,clear:INSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDcount10;ARCHITECTUREaOFcount10ISSIGNALq_temp:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(clk)BEGINIF(clk'eventandclk='1')THENIFclear='0'THENq_temp<="0000";ELSIFq_temp="1

4、001"THENq_temp<="0000";ELSEq_temp<=q_temp+1;ENDIF;ENDIF;ENDPROCESS;q<=q_temp;ENDa;数码管LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYseg7_1ISPORT(A:INSTD_LOGIC_VECTOR(3DOWNTO0);LED7S:OUTSTD_LOGIC_VECTOR(6DOWNTO0);CAT:OUTSTD_LOGIC_VE

5、CTOR(5DOWNTO0));ENDseg7_1;ARCHITECTUREONEOFseg7_1ISBEGINCAT<="011111";PROCESS(A)BEGINCASEAISWHEN"0000"=>LED7S<="0111111";--X"3F"->0WHEN"0001"=>LED7S<="0000110";--X"06"->1WHEN"0010"=>LED7S<="1011011";--X"5B"->2WHEN"0011"=>LED7S<="1001111";--X"4F"->3WHEN"0100"=>

6、LED7S<="1100110";--X"66"->4WHEN"0101"=>LED7S<="1101101";--X"6D"->5WHEN"0110"=>LED7S<="1111101";--X"7D"->6WHEN"0111"=>LED7S<="0000111";--X"07"->7WHEN"1000"=>LED7S<="1111111";--X"7F"->8WHEN"1001"=>LED7S<="1101111";--X"6F"->9WHEN"1010"=>LED7S<="1110111";--X"77"->

7、10WHEN"1011"=>LED7S<="1111100";--X"7C"->11WHEN"1100"=>LED7S<="0111001";--X"39"->12WHEN"1101"=>LED7S<="1011110";--X"5E"->13WHEN"1110"=>LED7S<="1111001";--X"79"->14WHEN"1111"=>LED7S<="1110001";--X"71"->15WHENOTHERS=>NULL;ENDCASE;ENDPROCESS;END;合成LIBRARYIEEE;USEI

8、EEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYabcISPORT(CLK:INSTD_LOGIC;CLEAR:INSTD_LOGIC;OP:OUTSTD_LOGIC_VECTOR(6DOWNTO0);CAT:OUTSTD_LOGIC_VECTOR(5DOWNTO0));ENDabc;A