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1、CPLDandMCUDescriptionThispaperstudiesontheeliminationofthecompetitiveandnarrowpulseinterferenceandonthereliabilityoftheresetcircuitinCPLDdesign.Methodsofadditionaltrigger,delaysuperposition,andlargerloopfeedbackareintroduced.Thecorrespondingexamplesarediscusseddetailedly.Thereliabilityproblemsof
2、thecircuitsinCPLDdesignaresolvedeffectively.CPLDhasbeenwidelyusedinthedesignofelectroniccircuitsandsystembecauseofitsflexibility,modifiability,andshortdevelopmentcycle.ThereinevitablyexistunreliablefactorsinCPLDdesignsuchascompetitiveinterference,narrowpulseinterference,andfalsetigger[1.Thispape
3、rstudiesthereliabilityproblemsbyexamplesandintroducescorrespondingprocessmethods.Theresultsaresatisfied.Anti-interferenceDesignofComplicatedCircuits.Acomplicatedpulsesignalgeneratorcanbeimplementedinblockdiagramasshowninfig..1.Where,allblockscanbeintegratedinCPLDexceptthewaveformdatastorage,inwh
4、ichallturntimeandcorrespondingstatearestored.AnEPROMcanbeused,twobytesforeachturntimeandstate.TheactivecrystaloscillatorisusuallyusedforCPLDastheclocksignal,becauseitsfrequencyishigh,thedividerisnecessarytoreducetheclocksignaltoanallowedfrequency.CounterⅠisatimerunitineachperiod.CounterⅡisaaddre
5、sspointer,indicatingtheaddresstobeaccessedcurrently.Thedatelatchrecordstheturnoftheoutputsignal.Theencoderproducesthetriggeringsignalsofthedatalatchanthestatelatch.Theperiodiccontrolsignalisresetofthedividerandtwocounters,andisclockofadditivecountertocontrolhighaddressoftheEPROMiftheoutputsignal
6、isdifferentbetweenperiodic.CounterⅠcountsfrom0toeachperiodic.Whenitscountedvalueequalsthedatainthedatalatch,theoutputofthecomparerturnshighlevel,andtheoutputtriggeristriggered,heoutputsignalturnsfollowingtheoutputofthestatelatch.Atthesametime,theNANDgateopens,theclocksignalactsonthecounterⅡandth
7、eencoder.Attherisingedge,thecounterⅡplusbyⅠ,thedatalatchandstatelatchlockmewdata,thenextturntimeandstatefromERROM.Theoutputofthecomparerrecoverslowlevel.Anoutputsignalturnanddatapresetcompleted.Apparently,aslongasthetimeandt
