VHDL的数字频率计实现

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1、5us转换为2slibraryieee;useieee.std_logic_1164.all;entityfdivisport(clk:instd_logic;q:outstd_logic);endfdiv;architectureaoffdivisbeginprocess(clk)variablecnt:integerrange0to199999;variableff:std_logic;beginifclk'eventandclk='1'thenifcnt<199999thencnt:=cnt+1;elsecnt

2、:=0;ff:=notff;endif;endif;q<=ff;endprocess;enda;20MHz转换成1Hzlibraryieee;useieee.std_logic_1164.all;entityfdivisport(clk:instd_logic;q:outstd_logic);endfdiv;architectureaoffdivisbeginprocess(clk)variablecnt:integerrange0to99999;variableff:std_logic;beginifclk'eve

3、ntandclk='1'thenifcnt<99999thencnt:=cnt+1;elsecnt:=0;ff:=notff;endif;endif;q<=ff;endprocess;enda;libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitycounter10isPort(clk:inSTD_LOGIC;clr:inSTD_LOGIC;en:inSTD_LOG

4、IC;count:outSTD_LOGIC_VECTOR(3downto0);cn_out:outSTD_LOGIC);endcounter10;architectureBehavioralofcounter10isSIGNALq:STD_LOGIC_VECTOR(3downto0);beginprocess(clk,clr,en)beginifclr='1'thenq<="0000";elsifclk'eventandclk='1'thenifen='1'thenifq<9thenq<=q+1;elseq<="00

5、00";endif;endif;endif;endprocess;process(q)beginifq=9thencn_out<='1';elsecn_out<='0';endif;endprocess;count<=q;endBehavioral;libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityload1isPort(load:inSTD_LOGIC;din

6、:inSTD_LOGIC_VECTOR(23downto0);dout:outSTD_LOGIC_VECTOR(23downto0));endload1;architectureBehavioralofload1isbeginbeginifload'eventandload='1'thendout<=din;endif;endprocess;endBehavioral;libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.

7、STD_LOGIC_UNSIGNED.ALL;entityledisa:outSTD_LOGIC;b:outSTD_LOGIC;c:outSTD_LOGIC;d:outSTD_LOGIC;e:outSTD_LOGIC;f:outSTD_LOGIC;g:outSTD_LOGIC);endled;architectureBehavioralofledisbeginprocess(d_in)typedata_outisarray(0to6)ofstd_logic;variableoutp:data_out;begincas

8、ed_iniswhen"0000"=>outp:="1110010";when"0001"=>outp:="0110000";when"0010"=>outp:="1101101";when"0011"=>outp:="1111001";when"0100"=>outp:="0110011";when"0101"=>outp:="1011011