VHDL计时器程序

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1、libraryieee;useieee.std_logic_1164.all;entityclkgenisport(clk:instd_logic;newclk:outstd_logic);endentityclkgen;architectureartofclkgenissignalcnter:integerrange0to10#29999#;beginprocess(clk)isbeginifclk'eventandclk='1'thenifcnter=10#29999#thencnter<=0;elsecnter<=c

2、nter+1;endif;endif;endprocess;process(cnter)isbeginifcnter=10#29999#thennewclk<='1';elsenewclk<='0';endif;endprocess;endarchitectureart;libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycnt6isport(clk:instd_logic;clr:instd_logic;ena:instd

3、_logic;cq:outstd_logic_vector(3downto0);carry_out:outstd_logic);endentitycnt6;architectureartofcnt6issignalcqi:std_logic_vector(3downto0);beginprocess(clk,clr,ena)isbeginifclr='1'thencqi<="0000";elseifclk'eventandclk='1'thenifena='1'thenifcqi="0101"thencqi<="0000"

4、;elsecqi<=cqi+'1';endif;endif;endif;endprocess;cq<=cqi;endarchitectureart;libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycnt10isport(clk:instd_logic;clr:instd_logic;ena:instd_logic;cq:outstd_logic_vector(3downto0);carry_out:outstd_logi

5、c);endentitycnt10;architectureartofcnt10issignalcqi:std_logic_vector(3downto0);beginprocess(clk,clr,ena)isbeginifclr='1'thencqi<="0000";elseifclk'eventandclk='1'thenifena='1'thenifcqi="1001"thencqi<="0000";elsecqi<=cqi+'1';endif;endif;endif;endprocess;process(cqi)

6、isbeginifcqi="0000"thencarry_out<='1';elsecarry_out<='0';endif;endprocess;cq<=cqi;endarchitectureart;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;ENTITYTIMESISPORT(CLR:INSTD_LOGIC;CLK:INSTD_LOGIC;ENA:INSTD_LOGIC

7、;DISPLAY:OUTSTD_LOGIC_VECTOR(7DOWNTO0);--七段码管显示输出SEG_SEL:BUFFERSTD_LOGIC_VECTOR(2DOWNTO0));--七段码管扫描驱动ENDENTITYTIMES;ARCHITECTUREARTOFTIMESISCOMPONENTCLKGENISPORT(CLK:INSTD_LOGIC;NEWCLK:OUTSTD_LOGIC);ENDCOMPONENTCLKGEN;COMPONENTCNT10ISPORT(CLK,CLR,ENA:INSTD_LOGIC;C

8、Q:OUTSTD_LOGIC_VECTOR(3DOWNTO0);CARRY_OUT:OUTSTD_LOGIC);ENDCOMPONENTCNT10;COMPONENTCNT6ISPORT(CLK,CLR,ENA:INSTD_LOGIC;CQ:OUTSTD_LOGIC_VECTOR(3DOWNTO0);C