第7章 引脚配置

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1、目录第7章引脚配置··············································································································17.1LPC176x引脚配置········································································································17.1.1引脚布局··········

2、······································································································17.1.2LPC1768引脚描述·································································································1LPC1700用户手册IIII第7章第7章引脚配置7.1LPC176x引脚配置7.

3、1.1引脚布局图7.1LPC176x引脚布局7.1.2LPC1768引脚描述表7.1引脚描述符号引脚类型描述P0口：P0口是一个32位I/O口。每个位都有独立的方向控制。P0P0[0]～P0[31]I/O口引脚的操作取决于引脚连接模块所选择的功能。P0口的引脚12、13、14和31不可用I/OP0[0]-通用数字输入/输出引脚P0[0]/RD1/TXD3/IRD1－CAN1接收器输入46[1]SDA1OTXD3－UART3的发送器输出I/O2C1数据输入/输出（不兼容I2C标准总线的开漏引脚）SDA1－II/O

4、P0[1]-通用数字输入/输出引脚P0[1]/TD1/RXD3/OTD1－CAN1发送器输出47[1]SCL1IRXD3－UART3的接收器输入I/O2C1时钟输入/输出（不兼容I2C标准总线的开漏引脚）SCL1－II/OP0[2]-通用数字输入/输出引脚。5V容差引脚，可提供数字I/O功能（带滞后TTL电平）和模拟输入。当配置为ADC输入时，引脚P0[2]/TXD0/AD0[7]98的数字部分禁能OTXD0-UART0的发送器输出IAD0[7]－A/D转换器0，输入7I/OP0[3]-通用数字输入/输出引脚。

5、5V容差引脚，可提供数字I/O功能（带滞后TTL电平）和模拟输入。当配置为ADC输入时，引脚P0[3]/RXD0/AD0[6]99的数字部分禁能IRXD0-UART0的接收器输入IAD0[6]－A/D转换器0，输入6LPC1700用户手册11第7章续上表符号引脚类型描述I/OP0[4]-通用数字输入/输出引脚I/OI2SRX_CLK-接收时钟。它由主机驱动，从机接收。该信号对应P0[4]/I2SRX_CLK/81[1]2于IS总线规范中的信号SCKRD2/CAP2[0]IRD2—CAN2接收器输入ICAP2[0

6、]-定时器2的捕获输入，通道0I/OP0[5]-通用数字输入/输出引脚I/OI2SRX_WS-接收字选择。它由主机驱动，从机接收。该信号对应P0[5]/I2SRX_WS/80[1]2于IS总线规范中的信号WSTD2/CAP2[1]OTD2—CAN2发送器输出ICAP2[1]-定时器2的捕获输入，通道1I/OP0[6]-通用数字输入/输出引脚I/OI2SRX_SDA-接收数据。它由发送器驱动，接收器读取。该信号P0[6]/I2SRX_SDA/79[1]2对应于IS总线规范中的信号SDSSEL1/MAT2[0]I/

7、OSSEL1—SSP1的从机选择OMAT2[0]-定时器2的匹配输出，通道0I/OP0[7]-通用数字输入/输出引脚I/OI2STX_CLK-发送时钟。它由主机驱动，从机接收。该信号对应P0[7]/I2STX_CLK/78[1]2于IS总线规范中的信号SCKSCK1/MAT2[1]I/OSCK1—SSP1的串行时钟OMAT2[1]-定时器2的匹配输出，通道1I/OP0[8]-通用数字输入/输出引脚I/OI2STX_WS-发送字选择。它由主机驱动，从机接收。该信号对应P0[8]/I2STX_WS/77[1]2S总

8、线规范中的信号WS于IMISO1/MAT2[2]I/OMISO1—SSP1的主机输入、从机输出OMAT2[2]-定时器2的匹配输出，通道2I/OP0[9]-通用数字输入/输出引脚I/OI2STX_SDA-发送数据。它由发送器驱动，接收器读取。该信号P0[9]/I2STX_SDA/76[1]2S总线规范中的信号SD对应于IMOSI1/MAT2[3]I/OMOSI1—SSP1的主机输出、从