《FPGA功耗优化》PPT课件

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1、PowerReductionTechniquesAlteraAsiaPacificRegionalSupportCenter2AgendaIntroductionPower-DrivenSynthesisPower-DrivenFittingClockPowerManagementLow-PowerDesignConclusion3Introduction67%22%11%CoreDynamicCoreStaticI/ODynamicPowerDominantFocusofPowerOptimization99Custo

2、merDesignsonStratixIIDevices4DynamicPowerOptimizationFlowAutomatic,butlessaccurateRequirestestbench,moreaccurateEvaluatePowerRTLSimulationPower-DrivenFitDesignPowerReportVectorlessEstimationHardwareMeasurementGate-LevelSimulation+PowerAnalyzerEstimateToggleRates

3、NormalorExtraeffortPower-DrivenSynthesisLowPowerDesignClockManagement5Power-DrivenSynthesisLocatedunder:“Analysis&SynthesisSettings”6Power-DrivenSynthesisOptionsExtraeffortMorepowerreductionMayincreasecompiletimeNormalcompilation(Default)StandardpowerreductionNoef

4、fectoncompiletimeordesignperformanceOffNooptimization7Power-DrivenSynthesisforRAMMemoryOptimizationNormalcompilationSettingPromoteRead/WriteEnableSignalstoClockRead/WriteEnableSignalsExtraeffortSettingPromoteRead/WriteEnableSignalstoClockRead/WriteEnableSignalsAND

5、Power-AwareMemoryBalancingMemoryBalancingconfiguresRAMforoptimalneedDefaultsettingselectsnarrow/deepermemoryconfigurationse.g.41kx4blocks(x4=narrow;1kwords=deeper)MW“MaximumDepth”optionselectswider/shallowRAMsforpowere.g.4256x16blocks(x16=wider;256words=shallow)Ac

6、cessonlyvalidmemoryslice,disabletherestDoesrequireadditionaldecoderandmuxlogichowever8RAMEnableOptimizationConvertread/writeenablestoclockread/writeenablesShutsRAMdownwhenunused,usinglesspowerSetRAMBlockType=“Auto”QuartusIIPowerOptimizerchoosesbestRAMblockconfigur

7、ationRAMCoreReadAddrReadDataReadEnWriteAddrWriteDataWriteEnReadClkWriteClk9MemoryBalancingPowerEfficientOption162:4Decoder4256x16M4KRAMsDefaultOption1641kx4M4KRAMs1kx16RAM10MaximumDepthParameter4kx36SimpleDual-PortmemoryimplementationusingM4KblocksFor128-deepM4Km

8、emoryblockdepth,extralogicpoweroutweighslowermemorypowerAverageDynamicPowersavingupto50%PowerPlayPowerAnalyzerresultsbasedonsimulationM4KBlocksConfigura