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1、外文资料HardwareandComputerOrganizationFrom:HardwareandComputerOrganization,ArnoldS.BergerFigure6.21isanexcerptformtedatasheetforanSDRAMmemorydevicefromMicronTechnology,Inc,asemiconductormemorymanufacturerlocatedinBoise,ID.ThetimingdiagramisfortheMT48LC128MXAfam
2、ilyofSDRAMmemories.Thedevicesare513Mbitpartsorganizedas4,8or16-bitwidedatapaths.The‘X’isaplaceholderfortheorganization(4,8or16bitwide).Thus,theMT48LC128M4A232m*isorganizedas32M*4,whiletheMT48LC128M4A2isorganizedas8M*16.Thesedevicesarefarmorecomplicatedinthei
3、roperationthenthesimpleSRAMmemorieswe’velookedatsofar.However,wecanseethefundamentalbrustbehaviorinFigure6.21.ThefieldsmarkedCOMMAND,ADDRESSandDQarerepresentedasbandofdata,ratherthanindividualbits.Thisisasimplificationthatallowsustoshowagroupofsignals,suchas
4、14addressbits,withouthavingtoshowthestateofeachindividualsignal.Thebandisusedtoshowwherethesignalmustbestableandwhereitisallowedtochang.Noticehowthesignalsareallsynchronizedtotherisingedgeoftheclock.OncetheREADcommandisissuedandtheaddressisprovidedforwhereth
5、eburstistooriginate,thereisatwoclockcyclelatencyansequentiallystoreddatainthechipwillthenbeavailableoneverysuccessiveclockcycle.Clearly,thisisfarmoreefficientthenreadingonebyteatatime.Whenweconsidercachememoriesingreaterdetail,we’llseethattheon-chipcachesare
6、alsodesignedtobefilledfromexternalmemoryinburstsofdata.Thus,weincurapenaltyinhavingtoset-uptheinitialconditionsforthedatatransferfromexternalmemorytotheon-chipcaches,butoncethedatatransferparametersareloaded,thememorytomemorydatatransfercantakeplacequiterapi
7、dly.Forthisfamilyofdevicesthedatatransfertakesplaceatamaximumclockrateof133MHz.NewerSDRAMdevices,calleddoubledatarate,orDDRchips,cantransferdataonboththerisingandfallingedgesoftheclock.Thus,aDDRchipwitha133MHzclockinputcantransferdataataspeedy266MHZ.Thesepar
8、tsaredesignated,forreasonsunknown,,asPC2700devices.AnySDRAMchipcapableofconformingtoa266MHZclockratearePC2700.ModernDRAMdesigntakesmanydifferentforms.We’vebeendiscussingSDRAMbecausethisisthemost
