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1、Constraining&AnalyzingSourceSynchronousInterface©2009AlteraCorporationAgendaAgendaBriefintroductiontowrite/readstructureSourceSynchronousIntroductionWriteconstraintsReadconstraintsMoreconstraintsTimingAnalysis©2009AlteraCorporationAltera,Stratix,Cyclone,MAX,HardC
2、opy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation2DDR2SDRAMWriteInterfaceDDR2SDRAMWriteInterfaceVCCInputDDRDQSClockSystemClockRegistersPLLGNDDDR2WRITEClockSDRAM-900PhaseShiftedDatatobeDDRDQWrittenRegistersPLLUsedtoGeneratethe90DegPhaseShiftBetweenDQandDQSSig
3、nals©2009AlteraCorporationAltera,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation3DDR2SDRAMReadInterfaceDDR2SDRAMReadInterfaceCoreIOEdq_oedq_outdq[7..0]AEDQQDClatchDBDQQDQDresynch_clockenaDataout[15..0]dqs_oedqs_outdqsDQSLogicBlockD
4、QSLocalBusPhaseShiftedClock©2009AlteraCorporationAltera,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation4BasicSourceSynchronousInterfaceBasicSourceSynchronousInterfaceSourceSynchronousinterfacesaretypicallyusedforhighspeeddatatransf
5、er.i.e.DDRmemory,HyperTransportbusandSPI©2009AlteraCorporationAltera,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation5InterfaceconstraintsInterfaceconstraintsClockconstraints−Definetheclocksusedintheinterface.Clockconstraintsdefine
6、theperiodandotherclockcharacteristics.i.e.offsetanduncertaintyInputoroutputdelayconstraints−Describetherequiredtimesfordatatobevalidattheinterface.TheinputandoutputdelayconstraintsarederivedfromtimingparameterssuchastSU,tHortCO.Timingexceptions−Controllaunchandlatche
7、dgesusedintiminganalysis.Timingexceptionsensurethatonlyvalidtimingpathsareanalyzed.©2009AlteraCorporationAltera,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation6InputandOutputDelayConstraintsInputandOutputDelayConstraintsSystem-cen
8、tricmethod−Tracedelay,tSU,tH,tCOandtCOminFPGA-centricmethod−skew??©2009AlteraCorporationAltera,Stratix,Cyclone,MAX,H
