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1、PackageInformationDatasheetforAlteraDevicesDS-PKG-16.5ThisdatasheetprovidespackageandthermalresistanceinformationforAltera®devices.Packageinformationincludestheorderingcodereference,packageacronym,leadframematerial,leadfinish(plating),JEDECoutlinereference,l
2、eadcoplanarity,weight,moisturesensitivitylevel,andotherspecialinformation.Thethermalresistanceinformationincludesdevicepincount,packagename,andresistancevalues.Thisdatasheetincludesthefollowingsections:■“DeviceandPackageCrossReference”onpage1■“ThermalResista
3、nce”onpage25■“PackageOutlines”onpage50fFormorepackageandthermalresistanceinformationaboutAlteradevicesthatarenotlistedinthisdatasheet,refertothePackageandThermalResistancepageoftheAlterawebsite.fForinformationabouttrays,tubes,anddrypacks,refertoAN71:Guidelin
4、esforHandlingJ-Lead,QFP,andBGADevices.fRoHS-compliantdevicesarecompatiblewithleaded-reflowtemperatures.Formoreinformation,refertoAltera’sRoHS-CompliantDevicesliteraturepage.DeviceandPackageCrossReferenceTable2throughTable26liststhedevice,packagetype,andnumbe
5、rofpinsforeachAlteradevice.Alteradevicesareavailableinthefollowingpackages:■Ball-GridArray(BGA)■CeramicPin-GridArray(PGA)■CeramicDualIn-LinePackage(CerDIP)■FineLineBGA(FBGA)■HybridFineLineBGA(HBGA)■MicroFineLineBGA(MBGA)■PlasticDualIn-LinePackage(PDIP)■Plast
6、icEnhancedQuadFlatPack(EQFP)■PlasticJ-LeadChipCarrier(PLCC)■PlasticQuadFlatPack(PQFP)■PowerQuadFlatPack(RQFP)■SmallOutlineIntegratedCircuitPackage(SOIC)■ThinQuadFlatPack(TQFP)©July2011AlteraCorporationPackageInformationDatasheetforAlteraDevices2PackageInform
7、ationDatasheetforAlteraDevicesDeviceandPackageCrossReference■UltraFineLineBGA(UBGA)■QuadFlatNo-LeadPackage(QFN)Table1liststheAlteradevicesandtheassociatedtablelocations.Table1.AlteraDeviceandPackageCrossReferenceAlteraDeviceTablelocationsArria®seriesFPGAs■Ar
8、riaGXDevices:Table2onpage3■StratixIIDevices:Table3onpage3Stratix®seriesFPGAs■StratixDevices:Table4onpage5■CycloneIIDevices:Table5onpage7Cyclone®seriesFPGAs■CycloneDevices:Table6onpage8■MAXVDevic
