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时间:2019-03-06
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1、(Ifyoureaditthensendcomments)AsynchronousEarlyOutputandEarlyAcknowledgeDual-RailProtocolsAthesissubmittedtotheUniversityofManchesterforthedegreeofMasterofPhilosophyintheFacultyofScience&EngineeringOctober2002CharlieBrejDepartmentofComputerScience1ContentsContents.........................
2、..........................................................................................2ListofFigures.........................................................................................................5ListofTables..................................................................
3、.........................................7Abstract...................................................................................................................8Declaration..............................................................................................................9
4、Copyright.................................................................................................................9TheAuthor............................................................................................................10Acknowledgements..............................
5、.................................................................11Chapter1:Introduction....................................................................................121.1Overview................................................................................................121.1.1
6、Justification..................................................................................121.2Synchronouslogic..................................................................................131.2.1Synchronouslogicconstruction...................................................131.
7、2.2Synchronouspipelineproperties..................................................131.3Asynchronouscircuits............................................................................141.3.1Whatisasynchronouslogic?........................................................14
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