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1、654321Notes:1)ActiveLowSignalsNamesendinBor_BDD2)PCIEdgeConnectorP1iskeyedas3.3VONLY3)+IOVforPCIedgeconnectoriswiredto3.3V4)Ref.Sheet6:PCIeCEMSpec,Pg.56footnotes:-BydefaultthePETpxandPETnxpinsshallbeconnectedtothePCIExpresstransmitterdifferentialpaironthesystemboard,andthePCIExp
2、ressreceiverpairontheadd-incard-BydefaultthePERpxandPERnxpinsshallbeconnectedtothePCIExpressreceiverdifferentialpaironthesystemboard,andthePCIExpresstransmitterpairontheadd-incardCCBBML555EngineeringRev04(4theng.spin)willbeProductionRev01forcustomerReleaseML555PCB:AALatestSchema
3、ticsRevision:XilinxRev01_10-30-06TITLESCHEM,ML555PCIEPCIPCI-XPCB,1280389XilinxPCBSchematicNumber:0381219SIZEDWGNOREVC038121901DRAWNBYSCALESHEETofDAVIDNAYLOR13710-30-2006_10:436543216543211.ML555SchematicSheetCoverPage2.ML555SchematicSheetList(thispage)3.P1aPCI/PCI-X3.3VEdgeConne
4、ctor,32-bitportion4.P1bPCI/PCI-X3.3VEdgeConnector,64-bitextension5.PCI/PCI-XP1FPGAI/F,3.0VBanks11,13,15DD6.PCIeEdgeConn.P13,PCIeI/FMGT'sX0Y0,X0Y1,X0Y2,X0Y37.MGTX0Y0,X0Y1,X0Y2,X0Y3Power&Filtering8.SFP1(J3),SFP2(J4)OpticalI/FConnectors9.MGTX0Y4SFP1&2I/F,U2ClockMux10.J5SATAConn,MGT
5、X0Y5SATAI/F,J6-J9SMAConns,U3ClockMux11.Y1Osc.125MHzLVDS,U11ClockMux12.U1PlatformFlash,P5JTAGConn,Y2Osc33MHzCMOS,U2PCIClkBuffer13.U6CPLD,Reset&ProgPush-Buttons14.Banks18,19P32,P33GPIOSamtecConnectors15.Banks1,2PFI/F,GPIOI/F,USBI/FCC16.Bank3GCLKI/F,misc.CLKI/F,Y2Osc.200MHzLVPECL,J
6、10&J11Clk.SMA17.J15,J162x32EPHYBERGHEADERS,J1USB-BConn,U5USBI/F18.Bank12BERGEPHYI/F,Bank20BERGHDR,U6CPLDI/F19.J2200-pin1.8VDDR2SODIMMSocket20.DDR2MemoryTerminationResistors21.Banks17and21DDR2SODIMMSocketI/F22.Banks4and22DDR2SODIMMSocketI/F23.Bank0JTAGandModeI/F24.U8ClockSynthesi
7、zer1-MemoryI/F25.U7ClockSynthesizer2-SATAandSFPI/FBB26.FPGAPowerConnections:VCCINT1.0V,VCCAUX2.5V,GND27.UnusedMGT'sXC5VLX110T28.UnusedXC5VLX110TBanks5,6,23,2529.VoltageRegulatorsVR1,VR2,VR330.VoltageRegulatorsVR4,U12,U13,U1431.MGTVoltageRegulatorsVR5,VR6,VR732.DecouplingCaps:12V
8、,5V,3.3V33.DecouplingCaps:2.5VVccaux,2.5VVcco34
