16位乘法器学习笔记(verilog语言源程序仿真程序)

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1、LCD1602显示源程序如下：modulelcdl602(inputelk,//60Minputrst_n5outputlcd_p,//BacklightSource+led屏幕背光outputlcd_n,//BacklightSource・outputreglcd_rs,//():writeorder;1:writedataoutputlcd_rw,//0:writcdata;1:readdataoutputreglcd_en,//negedge在lcd_en卜•降沿需保证数据有效outputreg[7:0Jlcd_data);mux16m

2、ul(.rst_n(rst_n)vclk(clk)5

3、结果显示wire[31:0]data2;wire[7:0]addr;//writeaddresswirestart.done;assigndata.rO=8'h30+data0L7:0];//8'h30在LCD1602上显示值为0。assigndata_rl=8*h30+data1[7:0J;assigndata_r2=8'h30+data2[7:0];//addressassignaddr=8fh8O;//led1602clk_enreg[31:0]ent;reglcd_clk_en;always@(posedgeelkornegedger

4、st_n)beginif(!rst_n)beginent<=VbO;lcd_clk_en<=1b0;elseif(cnt==32'h24999)//600usbeginlcd_clk_en<=lrbl;ent<=1'bO;endelsebeginent<=ent+Pbl;lcd_clk_en<=PbO;endendled1602displaystatereg[6:0]state;always@(posedgeelkornegedgerst_n)beginif(!rst_n)beginstate<=l*bO;lcd_rs<=1'b();lcd_

5、cn<=1'bO;lcd_data<=VbO;endbegincasc(statc)//6*d0:begininitstatelcd」s<=fbO;lcd_en<=l*bl;lcd_data<=Mode_Set;〃进入功能设置模式，“31”：数据总线8位，显示一行。6幻点阵/每字符state<=state+Pdl;end6rd1:beginlcd_en<=l*b0;//lcd_en变低电平，使led_en出现下降沿state<=state+fdl;end6'd2:beginlcd_rs<=l'b();lcd_cn<=l'bl;lcd_data

6、<=Cursor_Set;//光标设置：光标右移一格，一FLAC值加state<=state+l'dl;end6rd3:beginlcd_en<=1'bO;state<=state+I'd1;end6*d4:beginlcd_rs<=1'bO;lcd_en<=Lbl;lcd_data<=Address_Se(;〃模式设置：写入新数据后光标右移,AC自增1state<=state+fdl;end6*d5:beginlcd_en<=1'bO;state<=state+fdl;end6rd6:beginlcd_rs<=I'bO;lcd_en<=l'

7、bl;led.data<=Clcar_Sct;〃清屏操作：0x01state<=state+fdl;end6*d7:beginlcd_en<=1'bO;state<=state+fdl;end//workstate6*d8:beginlcd_rs<=1'bO;lcd_cn<=l'bl;lcd_data<=addr;//writeaddrstate<=state+l*dl;end6'd9:beginlcd_cn<=1'bO;state<=state+lfdl;end6*dl0:beginlcd_rs<=l'bl;lcd_cn<=l'bl;lcd

8、_data<=MRM;//writedatastate<=state+l*dl;6fd11:beginlcd_en<=1'bO;state<=state+I'dI;