n2cpu_nii51005

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1、1.SDRAMControllerCoreNII51005-9.1.0CoreOverviewTheSDRAMcontrollercorewithAvalon®interfaceprovidesanAvalonMemory-Mapped(Avalon-MM)interfacetooff-chipSDRAM.TheSDRAMcontrollerallowsdesignerstocreatecustomsystemsinanAltera®devicethatconnecteasilytoSDRAMchips.TheSDRAMcont

2、rollersupportsstandardSDRAMasdescribedinthePC100specification.SDRAMiscommonlyusedincost-sensitiveapplicationsrequiringlargeamountsofvolatilememory.WhileSDRAMisrelativelyinexpensive,controllogicisrequiredtoperformrefreshoperations,open-rowmanagement,andotherdelaysandc

3、ommandsequences.TheSDRAMcontrollerconnectstooneormoreSDRAMchips,andhandlesallSDRAMprotocolrequirements.Internaltothedevice,thecorepresentsanAvalon-MMslaveportthatappearsaslinearmemory(flataddressspace)toAvalon-MMmasterperipherals.ThecorecanaccessSDRAMsubsystemswithva

4、riousdatawidths(8,16,32,or64bits),variousmemorysizes,andmultiplechipselects.TheAvalon-MMinterfaceislatency-aware,allowingreadtransferstobepipelined.Thecorecanoptionallyshareitsaddressanddatabuseswithotheroff-chipAvalon-MMtri-statedevices.Thisfeatureisvaluableinsystem

5、sthathavelimitedI/Opins,yetmustconnecttomultiplememorychipsinadditiontoSDRAM.TheSDRAMcontrollercorewithAvaloninterfaceisSOPCBuilder-readyandintegrateseasilyintoanySOPCBuilder-generatedsystem.Thischaptercontainsthefollowingsections:■“FunctionalDescription”onpage1–2■“D

6、eviceSupport”onpage1–5■“InstantiatingtheCoreinSOPCBuilder”onpage1–5■“HardwareSimulationConsiderations”onpage1–7■“SoftwareProgrammingModel”onpage1–10■“Clock,PLLandTimingConsiderations”onpage1–10©November2009AlteraCorporationQuartusIIHandbookVersion9.1Volume5:EmbeddedP

7、eripherals1–2Chapter1:SDRAMControllerCoreFunctionalDescriptionFunctionalDescriptionFigure1–1showsablockdiagramoftheSDRAMcontrollercoreconnectedtoanexternalSDRAMchip.Figure1–1.SDRAMControllerwithAvalonInterfaceBlockDiagramAlteraFPGAClockPLLSDRAMClockSourcePhaseShiftCo

8、ntrollerClockSDRAMControllerCoreSDRAMChip(PC100)clkckeclockaddrbaaddressAvalon-MMslaveControlcsinterfacedata,controlLogiccastoon-ch