FLEX vs J750 .pdf

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1、IntroducingIntroducingtheTeradynetheTeradyneFLEXFLEXTestSystemTestSystemanditdifferencestoJ750anditdifferencestoJ750BecausetechnologyneverstopsBecausetechnologyneverstopsIntroducingtheFLEXFLEXIntroduction2/20042IntegratingTeradyne’sStrengths•BreakthroughR&D•Applicationsexpertise•Analoginstrumenta

2、tionperformance/breadth•3generationsofmixed-signaltestarchitectures•Breakthroughinmixed-signalSOCeconomics•Lowcost,CMOS-baseddesign•IG-XLsoftwareforease-of-use,compatibility•IG-XLsoftwareease-of-use•Analoginstrumentationbreadthandperformance•Highinstrumentdensity•4thgenerationmixed-signalarchitec

3、tureFLEXIntroduction2/20043UniversalSlotTestHeadDecentralizedSystemArchitectureHSD200DigitalDCInstrumentACInstrumentMicrowave12or24InstrumentSlotsUniversalSlotTestHead–ScalablePerformanceAirCooledslotsforoptimaleconomicsCableConnectDIBforflexibleconfigurationofsignaldeliveryDirectAccesstotheSync-

4、LinkandBackgroundDSPArchitectureIG-XLVerticalSlicedInstrumentSoftwareFLEXIntroduction2/20044FLEXishighlyconfigurableUniversalslottestheadHighdensitysingleboardinstruments48ch200MHzdigital24ch25Vdigital,75VPMU8choctalopamploop20ch30V/200mAdynamicDC6ch15AdynamicDC4ch75V/2AdynamicDC4ch90VdynamicDC4c

5、h15MHz,sourceandcapture4chVHFACsource&capture2chLowjitter1GHzclock11ch6GMicrowaveFuturecapabilityHighdensitydevicepowersupplyHighdensitydigitalOpenArchitecturedesignedinstrumentsHighdensityinstrumentsanduniversalslottestheadkeytofieldreconfigurabilityFLEXIntroduction2/20045J750tester64Channelspe

6、rBoard100MHz512/1024I/OPins4/16MegPerPinVectorMemorywithintegratedScanFlexiblePatternandTimingArchitecturex32TrueParallelTestFullsuiteofinstruments:⇒SCAN⇒ConverterTestOption⇒MemoryTestOption⇒HighVoltageDrivers⇒MixedSignalOptionFLEXIntroduction2/20046J750andFLEXInstrumentationcomparisonJ750F

7、LEX!Digital!Digital•64channelsdigital•48channelsdigital•Maximum16slots(max.1024channels)•Maximum24slots(max.1152channels)•Build-inoption•Build-inoption•digitalsignalsource/capture(DSIO)•digitalsignalsource/capture(DSSC