堆叠芯片级封装设计中信号完整性问题的分析

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1、图片目录图1多种多样的封装形式······················································································5图2覆晶接合（FlipChip）封装示意图·······························································6图3覆晶接合（FlipChip）封装显微照片（来源Intel）···································6图4三层堆叠芯片级封装（S-CSP）示意图············

2、············································7图5三层堆叠芯片级封装（S-CSP）显微照片（来源Intel）····························8图6上升、下降时间的定义················································································10图7导体层上互连线方块电阻模型····································································14图8电

3、源、地网络未联通布线图范例································································15图9电源、地网络联通布线图范例····································································16图10数据线长匹配布线图范例··········································································16图11分支匹配布线图范例·····················

4、·····························································17图12信号屏蔽（shielding）布线图范例···························································18图13返回路径示意图及环路面积布线图范例··················································18图14CMOS反相器1-0工作原理与电流通路··············································

5、·····19图15CMOS反相器0-1工作原理与电流通路···················································20®图16AllegroPackageDesigner15.7WireBonding设计界面··························21®图17AllegroPackageDesigner15.7Routing设计界面····································22图18AnsoftLinks4.0操作界面································

6、···········································22图19Q3DExtractor7操作界面··········································································23图20HSPICE操作界面·······················································································24图21实验设计方案封装形式示意图····························

7、······································27图22数据线长匹配测试电路设计图··································································28图23数据线长匹配基板布线设计图··································································28图24数据线长匹配三维模型图························································