[信息与通信]verilog_coding_style

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1、VerilogCodingStyleVerilogHDLCodingRules42of42Version0.1VerilogCodingStyle1.IntroductionThegeneralcodingstandardspertaintodesigngenerationanddealwithnamingconventions,documentationofthecodeandtheformat,orstyle,ofthecode.Conformitytothesestandardssimplifiesreusebydescribinginsightthatisabsen

2、tfromthecode,makingthecodemorereadableandassuringcompatibilitywithmosttools.Anyexceptionstotherulesspecifiedinthisstandard,exceptasnoted,mustbejustifiedanddocumented.Themethodologystandardspromotereusebyensuringahighadaptabilityamongapplications.Theintentofthisdocumentistoensurethatthegate

3、levelimplementationisidenticaltotheHDLcodeasitisunderstoodbyastandardVerilogsimulator.Partitioningcanaffecttheeasewithwhichamodelcanbeadaptedtoanapplication.Themodelingcomplexbehaviorsectiondealswithstructuresthataretypicallydifficulttoaddresswellinasynthesisenvironmentandareneededtoensure

4、pre-andpost-synthesisconsistency.Thesestandardsapplytobehavioralaswellassynthesizablecode.2ReferenceInformation2.1DocumentedReferences1.ReuseMethodologyManualforSystem-on-a-ChipDesigns,M.Keating,P.Bricaud,KluwerAcademicPublishers,2ndEdition,1999.2.2TerminologyHDL:HardwareDescriptionLanguag

5、eMTBF:MeanTimeBetweenFailuresPLL:PhaseLockedLoopRTL:RegisterTransferLevel3NamingConventions42of42Version0.1VerilogCodingStyle3.1FileNamingRULE3.1OnedesignunitperfileAfilemustnotcontainmorethanonedesignunit.Everythingcontainedinadesignunitmustbecompletelycontainedinasinglemodule/endmoduleco

6、nstruct.Reason:Simplifydesignmodifications.RULE3.2FilenamingconventionsThefilenameisthesamewiththeblockname,andshouldbecomposedinthefollowingway:.where:isthenameofthedesignunit(i.e.,modulename).signifiesthatitisaVerilogfile:.vVerilogfileforRTL.vgVe

7、rilogfileforGateLevelDesign.vhdforvhdlfile.Reason:Simplifyunderstandingthedesignstructure,andfilecontents.Example:spooler.vSynthesizableVerilogcodeformodulespoolerNote:RefertothedesignBlockDeliverablessectionformodelnamingconventions.RULE3.3AnaloganddigitalVer