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1、//megafunctionwizard:%ALTPLL%//GENERATION:STANDARD//VERSION:WM1.0//MODULE:altpll//============================================================//FileName:clk_ctrl.v//MegafunctionName(s)://altpll////SimulationLibraryFiles(s)://altera_mf//============================================
2、================//************************************************************//THISISAWIZARD-GENERATEDFILE.DONOTEDITTHISFILE!////11.0Build20807/03/2011SP1SJFullVersion//************************************************************//Copyright(C)1991-2011AlteraCorporation//Youruseo
3、fAlteraCorporation'sdesigntools,logicfunctions//andothersoftwareandtools,anditsAMPPpartnerlogic//functions,andanyoutputfilesfromanyoftheforegoing//(includingdeviceprogrammingorsimulationfiles),andany//associateddocumentationorinformationareexpresslysubject//tothetermsandcondition
4、softheAlteraProgramLicense//SubscriptionAgreement,AlteraMegaCoreFunctionLicense//Agreement,orotherapplicablelicenseagreement,including,//withoutlimitation,thatyouruseisforthesolepurposeof//programminglogicdevicesmanufacturedbyAlteraandsoldby//Alteraoritsauthorizeddistributors.Ple
5、aserefertothe//applicableagreementforfurtherdetails.//synopsystranslate_off`timescale1ps/1ps//synopsystranslate_onmoduleclk_ctrl(areset,inclk0,c0,c1,c2,41locked);inputareset;inputinclk0;outputc0;outputc1;outputc2;outputlocked;`ifndefALTERA_RESERVED_QIS//synopsystranslate_off`endi
6、ftri0areset;`ifndefALTERA_RESERVED_QIS//synopsystranslate_on`endifwire[5:0]sub_wire0;wiresub_wire2;wire[0:0]sub_wire7=1'h0;wire[2:2]sub_wire4=sub_wire0[2:2];wire[0:0]sub_wire3=sub_wire0[0:0];wire[1:1]sub_wire1=sub_wire0[1:1];wirec1=sub_wire1;wirelocked=sub_wire2;wirec0=sub_wire3;
7、wirec2=sub_wire4;wiresub_wire5=inclk0;wire[1:0]sub_wire6={sub_wire7,sub_wire5};altpllaltpll_component(.areset(areset),.inclk(sub_wire6),.clk(sub_wire0),.locked(sub_wire2),.activeclock(),.clkbad(),.clkena({6{1'b1}}),.clkloss(),.clkswitch(1'b0),.configupdate(1'b0),.enable0(),.enabl
8、e1(),.extclk(),.extclkena({4{1'b1}}),41.
