veriloghdl实验串行数据检测

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1、0妥郵電參院VerilogHDL实验报告（六）系部名称：通信工程专业名称：通信工程班级：班内序号:学生姓名:实验内容：串行数据检测设计模块源代码：modulecheck(clk,rst,in,out);inputclk,rst;inputin;outputout;reg[3:0]state;regout;parameteridle=3'b000,state1=3*5001,state2=3,b010,state3=3'b011,state4=3,bl00,state5=3'bl01,state6=3,bll0,state7=3!bl11;always@(posedgeelkornegedger

2、st)讦(!rst)beginstate<=idle;endelsecase(state)idle:if(in=rbO)state<=statel;elsestate<=idle;state1:if(in==l'bl)state<=state2;elsestate<=state1;state2:if(in=Tbl)state3:state<=state3;elsestate<=state1;if(in==rbO)state<=state4;elsestate<=idle;state4:if(in__fbl)state<=state5;state5:elsestate<=statel;if(in

3、==l'bO)state<=state6;elsestate<=state3;state6:if(in==l'bl)state<=state7;elsestate<=statel;state7:state<=idle;default:state<=idle;endcasealways@(posedgeelkornegedgerst)beginif(!rst)out<=TbO;elseif(state==state7)out<=Tbl;elseout<=rbO;endendmodule二测试模块modulejiance;regelk,rst;reg[23:0]in;wireout;wire[2:

4、0]state;wirex,z;checkwe(clk,rst,in,out);assignx=in[23];always#10clk=〜clk;always@(posedgeelk)in={in[22:0],in[23]};initialbegin$monitor($time,nout=%bH,out);clk=0;rst=l;#2rst=O;#50rst=1;#50rst=O;in^WOll1111111001011010;#500$stop;endendmodule三输出结果刊0卄平啊应"0卄1餐宓［.刖0廿m^zf桐/^r