星载电子标准化总线接口底层模块设计

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1、AbstractAbstractStandardizedbusinterfaceforsatelliteelectronicsisthepreconditiontoachievingOperationallyResponsiveSpace.Ithasstrategicsignificanceforspaceexplorationandintelligencecollectioninthefuture.Improvingthespeedofresponseisoneofthekeypointstowinninginthefuturewar.Itisveryim

2、portanttoensuretheresponsivesatellitebeingrapidlydesigned,manufactured,testedandlaunched.Researchofsatelliteelectronicbusinterfacestandardizationisfocusedbymanycountries.Thebottomcommunicationmoduleofstandardizedbusinterfaceisdesignedinthispaper.FPGAisusedtoimplementthebasicfunctio

3、nsofthebottommodule.Thefollowingworkiscompleted:firstly,byanalyzingthedesignedstandardizedbusprotocol,areasonabledesignisachieved.Andsuitablebustransceiversarechosen.RS485chipisusedasthelow-speedchanneltransceiverandM-LVDSchipisusedasthe100Mbpshighspeedchanneltransceiver;Secondly,t

4、hetop-downdesignmethodisadoptedtodesignthebottommodule.Thedesignisachievedrespectivelybydividingthebottommoduleintoseveralsub-modules.Thismethodimprovedthedesignefficiencyandflexibility,saveddesigntimeandimprovedthesystemcapabilityandversatility.Itiseasilytojointwithothermoduleofth

5、einterface.Whentheerrorsarefound,theycanbemodifiedeasily.Themainsub-modulesincludethetransmissionmodule,receivermodule,frame/deframemodule,8b/10bcoder/decodermodule.Thirdly,thebasicprinciplesofclockdatarecoveryandrelatedissuesareintroduced,andthebasicworkprinciplesofPhase-LockedLoo

6、p(PLL)andDelay-Locked-Loop(DLL)areelaborated.Theoversamplingmethodischosen,andthetwophase-shiftclockscreatedbytheDigitalClockManagementisusedinFPGAassamplingclocktoachievethefunctionofdatarecovery.Finally,aintegratedtestsystemisusedtoverifythedesign.Theexperimentshowedthatthebottom

7、moduledesignofthestandardizedbusinterfaceinthispaperwasreasonableandeffective,itcanachievethebasicfunctionsofthestandardizedbusinterface.KeyWords:standardizedbusinterface，moduledesign，clockdatarecoveryII目录目录摘要.........................................................................

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