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1、面向IP核的布图规划与PowerPad的协同优化-II-万方数据IP-CoreOrintedFoorplanningandPowerPadCo-optimizationAbstractAsthesemiconductortechniqueentersthedeepsub-micronstage,thesupplyvoltageisfurtherreduced,andthemetalinterconnectsoccupymorechiparea.Besides,theincreasingIPcoresareintegratedi
2、ntoasinglechip.AllabovefactorsmaketheIRdrop(voltagedrop)problemsignificantatthepresentstage.Excessivevoltagedropmaycausethesupplyvoltagecannotmeetthechipdemand,degradechipperformanceandevenchipfails.ThetraditionalSoCdesignflowdealswiththeIRdropproblematthepost-layou
3、tstage,whichmaycomplextheflowandtimeconsumingwhenthedesigndoesnotmeettherequirements.Therefore,theIRdropproblemshouldbepaidmoreattentionandsolvedeffectivelyintheearlyphysicaldesigncycle.ByexploringtheSoCdesignflowandcharacteristicstooptimizethevoltagedropandaccelera
4、tetheCPUtime,weproposeaheuristicmethodwhichcanoptimizethefloorplanandpowerpadssimultaneously.TheproposedmethodisvalidatedbytestingtheMCNCbenchmarkcircuits.Thethesisismainlycomposedofthefollowingtwosections:1.Floorplanninghasagreatimpactonthecurrentdensitydistributio
5、nofpower/groundnetwork.Intermsofthevoltagedropproblem,especiallyforthosehighcurrentdensityIPcores,acurrentdensityawarefloorplanningalgorithmbasedonfastsimulatedannealingisproposed.AmodifiedSKB-treeispresentedtorepresentthefloorplan,whichfavorstomulti-objectiveoptimi
6、zationformultiplepowerpadsplaceddiagonally.Fromtheresults,althoughthemethodmakesarea,wirelengthincreaseby2.07%and2.66%comparedwiththetraditionalfloorplanning,thedistancebetweenhighcurrentdensityIPcoresandpowerpadsisoptimizedby65.43%.Therefore,theeffectiveresistancei
7、sreducedandthevoltagedropisoptimized.2.ThetranditionalSoCdesignflowiscomplexandlowefficient.Considingtheimpactofpowerpadonthedistributionofpower/groundnetwork,thepowerpadallocationalgorithmisproposedandembeddedintothefloorplanningalgorithmtoachieveco-optimization.Th
8、evolagedropestimationaccuracyisimprovedbyestablishingtheclose-to-realcurrentdensitymodel.Comparedtotranditionalflow,therearenovoltageviola
