基于vhdl时钟设计说明书

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1、12/24小时数字钟设计顶层图12/24小时数字钟设计顶层图二、模块和程序1、计数器25000libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityyourname_cnt25000isport(clk:instd_logic;clkout:outstd_logic);endyourname_cnt25000;architecturebavofyourname_cnt25000issignalcnt:inte

2、gerrange0to24999;beginprocess(clk)beginifclk'eventandclk='1'thenifcnt=24999thencnt<=0;elsecnt<=cnt+1;endif;ifcnt<12500thenclkout<='1';elseclkout<='0';endif;endif;endprocess;endbav;2、去抖模块libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all

3、;entityyourname_qudouisport(key_in,clk_1kHz:instd_logic;key_out:outstd_logic);endyourname_qudou;architecturebehavofyourname_qudouissignalcnt20:integerrange0to19;beginprocess(clk_1kHz,key_in)beginifclk_1kHz'eventandclk_1kHz='1'thenifcnt20=19thencnt20<=0;ke

4、y_out<=key_in;elsecnt20<=cnt20+1;endif;endif;endprocess;endbehav;3、万年历模块万年历顶层电路图①年月日星期模块libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityyourname_ymdxisport(preset:instd_logic;co:instd_logic;date:outstd_logic_vector(7downto0);mo

5、nth,year:outstd_logic_vector(7downto0);xingqi:outstd_logic_vector(3downto0));endyourname_ymdx;architecturebavofyourname_ymdxissignalyue:std_logic_vector(7downto0):="00000001";signalnian:std_logic_vector(7downto0):="00001100";signalri:std_logic_vector(7dow

6、nto0):="00001100";signalxingqi1:std_logic_vector(3downto0):="0010";signalcnt:std_logic_vector(7downto0):="00000000";signalqm:integerrange28to31;beginprocess(yue,nian)begincaseyueiswhen"00000001"=>qm<=31;when"00000010"=>if(nian(0)='0')and(nian(1)='0')thenq

7、m<=29;elseqm<=28;endif;when"00000011"=>qm<=31;when"00000100"=>qm<=30;when"00000101"=>qm<=31;when"00000110"=>qm<=30;when"00000111"=>qm<=31;when"00001000"=>qm<=31;when"00001001"=>qm<=30;when"00001010"=>qm<=31;when"00001011"=>qm<=30;when"00001100"=>qm<=31;wh

8、enothers=>null;endcase;endprocess;process(co,preset,xingqi1)beginifpreset='0'thenyue<="00000001";nian<="00001100";ri<="00001100";xingqi1<="0010";elseifco'eventandco='1'thenif(ri=qm)thenri<="00000001";ifxingqi1="0111