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1、Xilinx中ise原语的使用1、IBUFGDS输入全局时钟及DCM分频使用： IBUFGDS#(.DIFF_TERM(“FALSE”),//DifferenTIalTerminaTIon(Virtex-4/5,Spartan-3E/3A).IOSTANDARD(“DEFAULT”)//SpecifiestheI/Ostandardforthisbuffer)IBUFGDS_inst(.O(CLK_SYS),//Clockbufferoutput.I(CLKP_SYS),//Diff_pcloc
2、kbufferinput.IB(CLKN_SYS)//Diff_nclockbufferinput); DCM_BASE#(.CLKDV_DIVIDE(2.0),//Divideby:1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5//7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0or16.0.CLKFX_DIVIDE(3),//Canbeanyintegerfrom1to32.CLKFX_MULTIPLY(2),
3、//Canbeanyintegerfrom2to32.CLKIN_DIVIDE_BY_2(“FALSE”),//TRUE/FALSEtoenableCLKINdividebytwofeature.CLKIN_PERIOD(8.14),//(10.0),//Specifyperiodofinputclockinnsfrom1.25to1000.00.CLKOUT_PHASE_SHIFT(“NONE”),//SpecifyphaseshiftmodeofNONEorFIXED.CLK_FEEDBACK
4、(“1X”),//SpecifyclockfeedbackofNONE,1Xor2X.DCM_PERFORMANCE_MODE(“MAX_SPEED”),//CanbeMAX_SPEEDorMAX_RANGE.DESKEW_ADJUST(“SYSTEM_SYNCHRONOUS”),//SOURCE_SYNCHRONOUS,SYSTEM_SYNCHRONOUSor//anintegerfrom0to15.DFS_FREQUENCY_MODE(“LOW”),//LOWorHIGHfrequencymo
5、deforfrequencysynthesis.DLL_FREQUENCY_MODE(“LOW”),//LOW,HIGH,orHIGH_SERfrequencymodeforDLL.DUTY_CYCLE_CORRECTION(“TRUE”),//Dutycyclecorrection,TRUEorFALSE.FACTORY_JF(16’hf0f0),//FACTORYJFvaluesuggestedtobesetto16’hf0f0.PHASE_SHIFT(0),//Amountoffixedph
6、aseshiftfrom-255to1023.STARTUP_WAIT(“FALSE”)//DelayconfigurationDONEuntilDCMLOCK,TRUE/FALSE)DCM_BASE_inst(.CLK0(CLK0),//0degreeDCMCLKoutput.CLK180(CLK180),//180degreeDCMCLKoutput.CLK270(CLK270),//270degreeDCMCLKoutput.CLK2X(CLK2X),//2XDCMCLKoutput.CLK
7、2X180(CLK2X180),//2X,180degreeDCMCLKout.CLK90(CLK90),//90degreeDCMCLKoutput.CLKDV(clk4608),//DividedDCMCLKout(CLKDV_DIVIDE).CLKFX(clk),//DCMCLKsynthesisout(M/D).CLKFX180(CLKFX180),//180degreeCLKsynthesisout.LOCKED(LOCKED),//DCMLOCKstatusoutput.CLKFB(C
8、LK0),//DCMclockfeedback.CLKIN(CLK_SYS),//Clockinput(fromIBUFG,BUFGorDCM).RST(1’b0)//DCMasynchronousresetinput);2、ODDR、IDDR单边缘与双边缘触发的转换。 单边缘输入双边缘输出： ODDR#(.DDR_CLK_EDGE(“OPPOSITE_EDGE”),//“OPPOSITE_EDGE”or“SAME_EDGE”.INIT(1’b0),//Initialvalue
