等精度频率相位数字测量仪

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1、本科生毕业设计（论文）摘要频率、相位差检测是电子测量领域的最基本也是最重要的测量之一。频率信号抗干扰能力强、易于传输，可以获得较高的测量精度，所以测频率测相位差方法的研究越来越受到重视。本课题的等精度数字频率计设计，采用当今电子设计领域流行的EDA技术，以CPLD为核心，配合AT89C51单片机，实现了0.1Hz～1MHz信号频率的等精度频率测量及分辨力为0.1的相位测试。设计中用一块复杂可编程逻辑器件CPLD芯片EPM7128SLC84-15完成各种时序逻辑控制、计数功能。在Max+plusⅡ平台

2、上，用VHDL语言编程完成了CPLD的软件设计、编译、调试、仿真和下载。用AT89C51单片机作为系统的主控部件，实现整个电路的测试信号控制、数据运算处理、键盘扫描和控制数码管的显示输出。系统将单片机AT89C51的控制灵活性及CPLD芯片的现场可编程性相结合，不但大大缩短了开发研制周期，而且使本系统具有结构紧凑、体积小，可靠性高，测频范围宽、精度高等优点。本文详细论述了系统自上而下的设计方法及各部分硬件电路组成及单片机、CPLD的软件编程设计。达到了较高的测量精度和测量速度。关键词：频率计；相位差

3、；复杂可编程逻辑器件；单片机64本科生毕业设计（论文）AbstractInthefieldofelectronicmeasurement,thefrequencyandphasedifferencecheckingisoneofmostfundamentalandcriticallyimportantmeasuringmethods.Becausefrequencysignal,whichiseasilytransported,hasstrongresistancetothedisturbancea

4、ndcanbemeasuredwithhighprecision,researchonthemethodbymeasuringfrequencyandphasedifferencehavemoreandmoresignificanceintherealapplication.WiththehelpofCPLDandcooperatingwiththesinglechipcomputerAT89C51，thedigitalfrequencydesigninourprogramhaverealizedt

5、heprecisionmeasurementof0.1Hz～1MHzsignalfrequencybyadoptingthecurrentEDAtechniqueprevailingintheelectronicdesigns.Duringthedesign,achipEPM7128SLC84-15inCPLDfulfillstiminglogiccontrolandcountfunction.UndertheflatofMax+plusⅡ，throughVHDLlanguageCPLDsoftwa

6、redesign,compilation,debug,simulationanddownloadcanbecarriedout.ByuseoftheAT89C51singlechipcomputerasthemaincontrollingparts,theAT89C51realizestestsignalcontrolkeyboardscanandoutputdisplayofLED.ThesystemcombinesthecontrolflexibilityofAT89C51withprogram

7、mableperformanceofCPLD，sonotonlycanitshortentheperiodofthedevelopmentandresearch，butalsohastheadvantagesofcompactstructurelittlevolumehighreliabilitywidescopeandhighprecision.Thispaperhasparticularlydescribedthetop-to-bottomdesignmethodofthesystem,thec

8、ircuitcompositeofthehardwareandthesoftwareprogramdeviceofCPLDandsinglechipcomputer.UnderthetestenvironmentofthesystemdevelopedbyGW48-CKEDAexperiment,theprecisionandvelocityofthemeasurementhavebeenobtainedafterthesimulationandthetestofth